TroubleElectrical/FPGA_Uni
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Repaired Sign extender module again to ensure only combinational logic used

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(There was a compilation error before, also compiled and tested code on board)
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TroubleElectrical committed 2026-10-22 15:53:15 +11:00
1 parent 973b9260b6
commit 8b48084fa5
147 files changed
+413208 -106764
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Quartus/A2/output_files/assignment2.eda.rpt
+7 -7
View File
@@ -1,5 +1,5 @@
EDA Netlist Writer report for assignment2
Fri Oct 16 14:23:31 2026
Thu Oct 22 15:48:49 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Fri Oct 16 14:23:31 2026 ;
; EDA Netlist Writer Status ; Successful - Thu Oct 22 15:48:49 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
@@ -81,13 +81,13 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Fri Oct 16 14:23:29 2026
Info: Processing started: Thu Oct 22 15:48:46 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 693 megabytes
Info: Processing ended: Fri Oct 16 14:23:31 2026
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Info: Peak virtual memory: 750 megabytes
Info: Processing ended: Thu Oct 22 15:48:49 2026
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:04