TroubleElectrical/FPGA_Uni
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Repaired Sign extender module again to ensure only combinational logic used

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(There was a compilation error before, also compiled and tested code on board)
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TroubleElectrical committed 2026-10-22 15:53:15 +11:00
1 parent 973b9260b6
commit 8b48084fa5
147 files changed
+413208 -106764
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Quartus/A2/db/assignment2.tmw_info
+6 -6
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@@ -1,7 +1,7 @@
start_full_compilation:s:00:02:50
start_analysis_synthesis:s:00:00:22-start_full_compilation
start_full_compilation:s:00:06:49
start_analysis_synthesis:s:00:00:41-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:01:57-start_full_compilation
start_assembler:s:00:00:08-start_full_compilation
start_timing_analyzer:s:00:00:19-start_full_compilation
start_eda_netlist_writer:s:00:00:04-start_full_compilation
start_fitter:s:00:05:07-start_full_compilation
start_assembler:s:00:00:10-start_full_compilation
start_timing_analyzer:s:00:00:46-start_full_compilation
start_eda_netlist_writer:s:00:00:05-start_full_compilation