TroubleElectrical/FPGA_Uni
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Repaired Sign extender module again to ensure only combinational logic used

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(There was a compilation error before, also compiled and tested code on board)
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TroubleElectrical committed 2026-10-22 15:53:15 +11:00
1 parent 973b9260b6
commit 8b48084fa5
147 files changed
+413208 -106764
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Quartus/A2/db/assignment2.lpc.html
+7 -7
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@@ -146,13 +146,13 @@
<TR >
<TD >SIGNEXT</TD>
<TD >17</TD>
<TD >15</TD>
<TD >1</TD>
<TD >0</TD>
<TD >15</TD>
<TD >1</TD>
<TD >32</TD>
<TD >15</TD>
<TD >15</TD>
<TD >15</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
@@ -209,11 +209,11 @@
</TR>
<TR >
<TD >RAM</TD>
<TD >17</TD>
<TD >44</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >5</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>