Made addrwidth sizing consistent with the 2^N used everywhere

modules/ram.sv

@@ -3,7 +3,7 @@
 
 module ram #(addrwidth=9, datawidth=5)(
     input logic [0:0] clk,
-    input logic [2**addrwidth-1:0] addr,
+    input logic [addrwidth-1:0] addr,
     input logic [0:0] we,
     input logic [datawidth-1:0] data_in,
     output logic [datawidth-1:0] data_out