Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/sign_extender.sv

@@ -7,7 +7,11 @@ module sign_extender #(in_width=4, out_width=5)(
     output logic [2**out_width-1:0] ext_val
 );
     always_comb begin
-        assign ext_val = (op) ? {{(2**(out_width-in_width)){val[2**in_width-1]}}, val} : ({{(2**(out_width-in_width)){1'b0}}, val});
+        if (op) begin
+            assign ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
+        end else begin
+            assign ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
+        end
     end
 endmodule
 `endif