TroubleElectrical/FPGA_Uni
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TODO: Remove Shifter Code

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TroubleElectrical committed 2026-10-13 16:57:03 +11:00
1 parent 25a953cdc6
commit 80416e1f8a
70 files changed
+213 -270
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Quartus/A2/output_files/assignment2.map.rpt
+9 -9
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for assignment2
Tue Oct 13 16:18:22 2026
Tue Oct 13 16:47:37 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -63,7 +63,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Oct 13 16:18:22 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Oct 13 16:47:37 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
@@ -91,6 +91,7 @@ on the Quartus Prime software download page.
; Device ; 5CGXFC5C6F27C7 ; ;
; Top-level entity name ; assignment2 ; assignment2 ;
; Family name ; Cyclone V ; Cyclone V ;
; Maximum processors allowed for parallel compilation ; 2 ; ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
@@ -502,10 +503,9 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:18:11 2026
Info: Processing started: Tue Oct 13 16:47:26 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (20032): Parallel compilation is enabled and will use up to 2 processors
Info (12021): Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4
Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4
@@ -751,10 +751,10 @@ Warning (21074): Design contains 8 input pin(s) that do not drive logic
Info (21057): Implemented 40 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 8 input pins
Info (21059): Implemented 32 output pins
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings
Info: Peak virtual memory: 423 megabytes
Info: Processing ended: Tue Oct 13 16:18:22 2026
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 213 warnings
Info: Peak virtual memory: 425 megabytes
Info: Processing ended: Tue Oct 13 16:47:37 2026
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:25
Info: Total CPU time (on all processors): 00:00:23