diff --git a/Quartus/A2/assignment2.qsf b/Quartus/A2/assignment2.qsf index 05876ca..b847dba 100644 --- a/Quartus/A2/assignment2.qsf +++ b/Quartus/A2/assignment2.qsf @@ -36,7 +36,7 @@ # # -------------------------------------------------------------------------- # set_global_assignment -name VERILOG_MACRO QUARTUS_SYNTH - +set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CGXFC5C6F27C7 @@ -119,4 +119,6 @@ set_location_assignment PIN_AA23 -to out_seg_3[3] set_location_assignment PIN_AA22 -to out_seg_3[4] set_location_assignment PIN_AC24 -to out_seg_3[5] set_location_assignment PIN_AC23 -to out_seg_3[6] + + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/A2/db/assignment2.(60).cnf.cdb b/Quartus/A2/db/assignment2.(60).cnf.cdb new file mode 100644 index 0000000..e407939 Binary files /dev/null and b/Quartus/A2/db/assignment2.(60).cnf.cdb differ diff --git a/Quartus/A2/db/assignment2.(60).cnf.hdb b/Quartus/A2/db/assignment2.(60).cnf.hdb new file mode 100644 index 0000000..8f35b01 Binary files /dev/null and b/Quartus/A2/db/assignment2.(60).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.(61).cnf.cdb b/Quartus/A2/db/assignment2.(61).cnf.cdb new file mode 100644 index 0000000..0fb1298 Binary files /dev/null and b/Quartus/A2/db/assignment2.(61).cnf.cdb differ diff --git a/Quartus/A2/db/assignment2.(61).cnf.hdb b/Quartus/A2/db/assignment2.(61).cnf.hdb new file mode 100644 index 0000000..801e2e9 Binary files /dev/null and b/Quartus/A2/db/assignment2.(61).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.(62).cnf.cdb b/Quartus/A2/db/assignment2.(62).cnf.cdb new file mode 100644 index 0000000..627d115 Binary files /dev/null and b/Quartus/A2/db/assignment2.(62).cnf.cdb differ diff --git a/Quartus/A2/db/assignment2.(62).cnf.hdb b/Quartus/A2/db/assignment2.(62).cnf.hdb new file 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mode 100644 index 0000000..668fb20 Binary files /dev/null and b/Quartus/A2/db/assignment2.(69).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.(70).cnf.cdb b/Quartus/A2/db/assignment2.(70).cnf.cdb new file mode 100644 index 0000000..36eb393 Binary files /dev/null and b/Quartus/A2/db/assignment2.(70).cnf.cdb differ diff --git a/Quartus/A2/db/assignment2.(70).cnf.hdb b/Quartus/A2/db/assignment2.(70).cnf.hdb new file mode 100644 index 0000000..5a96447 Binary files /dev/null and b/Quartus/A2/db/assignment2.(70).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.asm.qmsg b/Quartus/A2/db/assignment2.asm.qmsg index 171a2a5..2e85e9c 100644 --- a/Quartus/A2/db/assignment2.asm.qmsg +++ b/Quartus/A2/db/assignment2.asm.qmsg @@ -1,6 +1,5 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868735615 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868735616 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:18:55 2026 " "Processing started: Tue Oct 13 16:18:55 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868735616 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1791868735616 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1791868735616 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1791868736314 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1791868740928 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "508 " "Peak virtual memory: 508 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868741112 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:19:01 2026 " "Processing ended: Tue Oct 13 16:19:01 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868741112 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868741112 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868741112 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1791868741112 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791870487985 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791870487986 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:48:07 2026 " "Processing started: Tue Oct 13 16:48:07 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791870487986 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1791870487986 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1791870487986 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1791870492963 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "516 " "Peak virtual memory: 516 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791870493147 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:48:13 2026 " "Processing ended: Tue Oct 13 16:48:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791870493147 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791870493147 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791870493147 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1791870493147 ""} diff --git a/Quartus/A2/db/assignment2.asm.rdb b/Quartus/A2/db/assignment2.asm.rdb index 6614f3a..4bdb4bf 100644 Binary files a/Quartus/A2/db/assignment2.asm.rdb and b/Quartus/A2/db/assignment2.asm.rdb differ diff --git a/Quartus/A2/db/assignment2.cmp.bpm b/Quartus/A2/db/assignment2.cmp.bpm index ac707fe..48f9ddd 100644 Binary files a/Quartus/A2/db/assignment2.cmp.bpm and b/Quartus/A2/db/assignment2.cmp.bpm differ diff --git a/Quartus/A2/db/assignment2.cmp.cdb b/Quartus/A2/db/assignment2.cmp.cdb index 0b65a82..5ab467d 100644 Binary files a/Quartus/A2/db/assignment2.cmp.cdb and b/Quartus/A2/db/assignment2.cmp.cdb differ diff --git a/Quartus/A2/db/assignment2.cmp.hdb b/Quartus/A2/db/assignment2.cmp.hdb index fa70b4a..8a5ef2f 100644 Binary files a/Quartus/A2/db/assignment2.cmp.hdb and b/Quartus/A2/db/assignment2.cmp.hdb differ diff --git a/Quartus/A2/db/assignment2.cmp.rdb b/Quartus/A2/db/assignment2.cmp.rdb index 3ca3351..8721530 100644 Binary files a/Quartus/A2/db/assignment2.cmp.rdb and b/Quartus/A2/db/assignment2.cmp.rdb differ diff --git a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd index 5b25938..b19b6d1 100644 Binary files a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd and b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd index 0778662..118df22 100644 Binary files a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd and b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A2/db/assignment2.eda.qmsg b/Quartus/A2/db/assignment2.eda.qmsg index 6f78e9e..404b261 100644 --- a/Quartus/A2/db/assignment2.eda.qmsg +++ b/Quartus/A2/db/assignment2.eda.qmsg @@ -1,6 +1,5 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868749469 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868749469 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:19:09 2026 " "Processing started: Tue Oct 13 16:19:09 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868749469 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791868749469 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791868749469 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1791868750209 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "assignment2.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/ simulation " "Generated file assignment2.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1791868750264 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868750313 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:19:10 2026 " "Processing ended: Tue Oct 13 16:19:10 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868750313 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868750313 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868750313 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1791868750313 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791870501332 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791870501333 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:48:21 2026 " "Processing started: Tue Oct 13 16:48:21 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791870501333 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791870501333 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791870501333 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "assignment2.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/ simulation " "Generated file assignment2.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1791870502164 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791870502214 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:48:22 2026 " "Processing ended: Tue Oct 13 16:48:22 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791870502214 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791870502214 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791870502214 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1791870502214 ""} diff --git a/Quartus/A2/db/assignment2.fit.qmsg b/Quartus/A2/db/assignment2.fit.qmsg index e837968..7c95c57 100644 --- a/Quartus/A2/db/assignment2.fit.qmsg +++ b/Quartus/A2/db/assignment2.fit.qmsg @@ -1,45 +1,44 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1791868704138 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1791868704138 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "assignment2 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"assignment2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1791868704143 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791868704223 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791868704223 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1791868704647 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1791868704678 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1791868704740 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 40 " "No exact pin location assignment(s) for 4 pins of 40 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1791868705016 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1791868711846 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868711948 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1791868711950 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791868711950 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791868711951 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1791868711951 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1791868711951 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1791868711952 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1791868711952 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1791868711952 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1791868711952 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868711988 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1791868718247 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1791868718248 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1791868718248 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1791868718249 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1791868718250 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1791868718250 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1791868718250 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1791868718253 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1791868718361 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868718828 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1791868719237 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1791868719488 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868719488 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1791868720212 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y24 X10_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36"} { { 12 { 0 ""} 0 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1791868726720 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1791868726720 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1791868726886 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1791868726886 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1791868726886 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868726888 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.06 " "Total time spent on timing analysis during the Fitter is 0.06 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1791868728510 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791868728549 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791868728999 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791868728999 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791868729690 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:05 " "Fitter post-fit operations ending: elapsed time is 00:00:05" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868733059 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1791868733343 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1337 " "Peak virtual memory: 1337 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868733957 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:18:53 2026 " "Processing ended: Tue Oct 13 16:18:53 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868733957 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868733957 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:42 " "Total CPU time (on all processors): 00:00:42" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868733957 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791868733957 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1791870458807 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "assignment2 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"assignment2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1791870458812 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791870458886 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791870458886 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1791870459290 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1791870459318 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1791870459367 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 40 " "No exact pin location assignment(s) for 4 pins of 40 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1791870459626 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1791870466242 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791870466323 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1791870466325 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791870466325 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791870466326 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1791870466326 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1791870466326 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1791870466326 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1791870466327 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1791870466327 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1791870466327 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791870466357 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1791870472309 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1791870472310 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1791870472310 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1791870472310 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1791870472311 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1791870472312 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1791870472312 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1791870472315 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1791870472410 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791870472792 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1791870472993 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1791870473221 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791870473222 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1791870473911 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y24 X10_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36"} { { 12 { 0 ""} 0 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1791870479436 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1791870479436 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1791870479598 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1791870479598 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1791870479598 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791870479600 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.04 " "Total time spent on timing analysis during the Fitter is 0.04 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1791870481216 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791870481250 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791870481680 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791870481680 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791870482327 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791870485530 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1791870485793 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1328 " "Peak virtual memory: 1328 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791870486389 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:48:06 2026 " "Processing ended: Tue Oct 13 16:48:06 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791870486389 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791870486389 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791870486389 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791870486389 ""} diff --git a/Quartus/A2/db/assignment2.hif b/Quartus/A2/db/assignment2.hif index 3e95992..8038934 100644 Binary files a/Quartus/A2/db/assignment2.hif and b/Quartus/A2/db/assignment2.hif differ diff --git a/Quartus/A2/db/assignment2.map.bpm b/Quartus/A2/db/assignment2.map.bpm index d524dcb..93a9597 100644 Binary files a/Quartus/A2/db/assignment2.map.bpm and b/Quartus/A2/db/assignment2.map.bpm differ diff --git a/Quartus/A2/db/assignment2.map.cdb b/Quartus/A2/db/assignment2.map.cdb index 7b7537f..769c318 100644 Binary files a/Quartus/A2/db/assignment2.map.cdb and b/Quartus/A2/db/assignment2.map.cdb differ diff --git a/Quartus/A2/db/assignment2.map.hdb b/Quartus/A2/db/assignment2.map.hdb index 92ca633..14538e5 100644 Binary files a/Quartus/A2/db/assignment2.map.hdb and b/Quartus/A2/db/assignment2.map.hdb differ diff --git a/Quartus/A2/db/assignment2.map.qmsg b/Quartus/A2/db/assignment2.map.qmsg index 82aada1..9ccbd2a 100644 --- a/Quartus/A2/db/assignment2.map.qmsg +++ b/Quartus/A2/db/assignment2.map.qmsg @@ -1,35 +1,34 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868691584 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868691585 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:18:11 2026 " "Processing started: Tue Oct 13 16:18:11 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868691585 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868691585 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868691585 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791868691904 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791868691904 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 13 13 " "Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "11 seven_seg " "Found entity 11: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg_4digit " "Found entity 12: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "13 assignment2 " "Found entity 13: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868701292 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791868701433 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(54) " "Verilog HDL or VHDL warning at assignment2.sv(54): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 54 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791868701435 "|assignment2"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701436 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701444 ""} -{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791868701453 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868701487 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868701487 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868701487 "|assignment2|rom:ROM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701493 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 68 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701496 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 74 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701500 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 77 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701508 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701514 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701520 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" { } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701526 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_4digit seven_seg_4digit:display " "Elaborating entity \"seven_seg_4digit\" for hierarchy \"seven_seg_4digit:display\"" { } { { "../../modules/assignment2.sv" "display" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701531 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg_4digit:display\|seven_seg:digit0 " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg_4digit:display\|seven_seg:digit0\"" { } { { "../../modules/seven_seg_4digit.sv" "digit0" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701535 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701572 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701574 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701575 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701577 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701579 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791868702092 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[0\] GND " "Pin \"out_seg_0\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[1\] GND " "Pin \"out_seg_0\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[2\] GND " "Pin \"out_seg_0\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[3\] VCC " "Pin \"out_seg_0\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[4\] GND " "Pin \"out_seg_0\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[5\] GND " "Pin \"out_seg_0\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[6\] VCC " "Pin \"out_seg_0\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[7\] GND " "Pin \"out_seg_0\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[0\] GND " "Pin \"out_seg_1\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[1\] VCC " "Pin \"out_seg_1\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[2\] GND " "Pin \"out_seg_1\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[3\] GND " "Pin \"out_seg_1\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[4\] VCC " "Pin \"out_seg_1\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[5\] VCC " "Pin \"out_seg_1\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[6\] GND " "Pin \"out_seg_1\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[7\] GND " "Pin \"out_seg_1\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[0\] GND " "Pin \"out_seg_2\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[1\] GND " "Pin \"out_seg_2\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[2\] GND " "Pin \"out_seg_2\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[3\] GND " "Pin \"out_seg_2\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[4\] GND " "Pin \"out_seg_2\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[5\] VCC " "Pin \"out_seg_2\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[6\] VCC " "Pin \"out_seg_2\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[7\] GND " "Pin \"out_seg_2\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[0\] GND " "Pin \"out_seg_3\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[1\] GND " "Pin \"out_seg_3\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[2\] VCC " "Pin \"out_seg_3\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[3\] VCC " "Pin \"out_seg_3\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[4\] GND " "Pin \"out_seg_3\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[5\] GND " "Pin \"out_seg_3\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[6\] GND " "Pin \"out_seg_3\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[7\] VCC " "Pin \"out_seg_3\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1791868702109 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791868702113 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791868702233 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868702233 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|clk[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[0\] " "No output dependent on input pin \"HID_Register\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[1\] " "No output dependent on input pin \"HID_Register\[1\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[2\] " "No output dependent on input pin \"HID_Register\[2\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[3\] " "No output dependent on input pin \"HID_Register\[3\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[4\] " "No output dependent on input pin \"HID_Register\[4\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_PC\[0\] " "No output dependent on input pin \"HID_PC\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_PC[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Hi_Low\[0\] " "No output dependent on input pin \"HID_Hi_Low\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Hi_Low[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791868702270 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791868702270 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791868702270 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791868702270 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 214 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "423 " "Peak virtual memory: 423 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868702288 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:18:22 2026 " "Processing ended: Tue Oct 13 16:18:22 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868702288 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868702288 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868702288 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868702288 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791870447003 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791870447004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:47:26 2026 " "Processing started: Tue Oct 13 16:47:26 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791870447004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791870447004 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791870447004 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1791870447329 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 13 13 " "Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "11 seven_seg " "Found entity 11: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg_4digit " "Found entity 12: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} { "Info" "ISGN_ENTITY_NAME" "13 assignment2 " "Found entity 13: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791870456035 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791870456035 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791870456176 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(54) " "Verilog HDL or VHDL warning at assignment2.sv(54): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 54 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791870456178 "|assignment2"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456179 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456190 ""} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791870456198 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791870456231 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791870456231 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791870456231 "|assignment2|rom:ROM"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456234 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 68 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456237 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 74 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456240 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 77 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456246 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456253 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456259 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" { } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456264 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_4digit seven_seg_4digit:display " "Elaborating entity \"seven_seg_4digit\" for hierarchy \"seven_seg_4digit:display\"" { } { { "../../modules/assignment2.sv" "display" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456270 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg_4digit:display\|seven_seg:digit0 " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg_4digit:display\|seven_seg:digit0\"" { } { { "../../modules/seven_seg_4digit.sv" "digit0" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456274 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456323 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791870456323 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456324 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791870456324 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456325 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791870456325 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456326 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791870456326 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791870456327 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791870456327 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791870456839 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[0\] GND " "Pin \"out_seg_0\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_0[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[1\] GND " "Pin \"out_seg_0\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_0[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[2\] GND " "Pin \"out_seg_0\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_0[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[3\] VCC " "Pin \"out_seg_0\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_0[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[4\] GND " "Pin \"out_seg_0\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_0[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[5\] GND " "Pin \"out_seg_0\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_0[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[6\] VCC " "Pin \"out_seg_0\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_0[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[7\] GND " "Pin \"out_seg_0\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_0[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[0\] GND " "Pin \"out_seg_1\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[1\] VCC " "Pin \"out_seg_1\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[2\] GND " "Pin \"out_seg_1\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[3\] GND " "Pin \"out_seg_1\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[4\] VCC " "Pin \"out_seg_1\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[5\] VCC " "Pin \"out_seg_1\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[6\] GND " "Pin \"out_seg_1\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_1[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[7\] GND " "Pin \"out_seg_1\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_1[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[0\] GND " "Pin \"out_seg_2\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[1\] GND " "Pin \"out_seg_2\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[2\] GND " "Pin \"out_seg_2\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[3\] GND " "Pin \"out_seg_2\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[4\] GND " "Pin \"out_seg_2\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[5\] VCC " "Pin \"out_seg_2\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[6\] VCC " "Pin \"out_seg_2\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_2[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[7\] GND " "Pin \"out_seg_2\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_2[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[0\] GND " "Pin \"out_seg_3\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_3[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[1\] GND " "Pin \"out_seg_3\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[2\] VCC " "Pin \"out_seg_3\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[3\] VCC " "Pin \"out_seg_3\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_3[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[4\] GND " "Pin \"out_seg_3\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_3[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[5\] GND " "Pin \"out_seg_3\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_3[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[6\] GND " "Pin \"out_seg_3\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[7\] VCC " "Pin \"out_seg_3\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791870456857 "|assignment2|out_seg_3[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1791870456857 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791870456860 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791870456986 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791870456986 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791870457018 "|assignment2|clk[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[0\] " "No output dependent on input pin \"HID_Register\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791870457018 "|assignment2|HID_Register[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[1\] " "No output dependent on input pin \"HID_Register\[1\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791870457018 "|assignment2|HID_Register[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[2\] " "No output dependent on input pin \"HID_Register\[2\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791870457018 "|assignment2|HID_Register[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[3\] " "No output dependent on input pin \"HID_Register\[3\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791870457018 "|assignment2|HID_Register[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[4\] " "No output dependent on input pin \"HID_Register\[4\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791870457018 "|assignment2|HID_Register[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_PC\[0\] " "No output dependent on input pin \"HID_PC\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791870457018 "|assignment2|HID_PC[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Hi_Low\[0\] " "No output dependent on input pin \"HID_Hi_Low\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791870457018 "|assignment2|HID_Hi_Low[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791870457018 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791870457019 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791870457019 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791870457019 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 213 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 213 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "425 " "Peak virtual memory: 425 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791870457029 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:47:37 2026 " "Processing ended: Tue Oct 13 16:47:37 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791870457029 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791870457029 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791870457029 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791870457029 ""} diff --git a/Quartus/A2/db/assignment2.map.rdb b/Quartus/A2/db/assignment2.map.rdb index a1c4a77..af6a078 100644 Binary files a/Quartus/A2/db/assignment2.map.rdb and b/Quartus/A2/db/assignment2.map.rdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.cdb b/Quartus/A2/db/assignment2.map_bb.cdb index d5574fb..b5c24ba 100644 Binary files a/Quartus/A2/db/assignment2.map_bb.cdb and b/Quartus/A2/db/assignment2.map_bb.cdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.hdb b/Quartus/A2/db/assignment2.map_bb.hdb index 2fd903e..a3a2097 100644 Binary files a/Quartus/A2/db/assignment2.map_bb.hdb and b/Quartus/A2/db/assignment2.map_bb.hdb differ diff --git a/Quartus/A2/db/assignment2.pre_map.hdb b/Quartus/A2/db/assignment2.pre_map.hdb index 934a41c..6f1af80 100644 Binary files a/Quartus/A2/db/assignment2.pre_map.hdb and b/Quartus/A2/db/assignment2.pre_map.hdb differ diff --git a/Quartus/A2/db/assignment2.rtlv.hdb b/Quartus/A2/db/assignment2.rtlv.hdb index cba2dcf..b868141 100644 Binary files a/Quartus/A2/db/assignment2.rtlv.hdb and b/Quartus/A2/db/assignment2.rtlv.hdb differ diff --git a/Quartus/A2/db/assignment2.sta.qmsg b/Quartus/A2/db/assignment2.sta.qmsg index 45b5b83..96f5912 100644 --- a/Quartus/A2/db/assignment2.sta.qmsg +++ b/Quartus/A2/db/assignment2.sta.qmsg @@ -1,61 +1,60 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868742624 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868742625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:19:02 2026 " "Processing started: Tue Oct 13 16:19:02 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868742625 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1791868742625 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta assignment2 -c assignment2 " "Command: quartus_sta assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1791868742625 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1791868742686 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1791868743231 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1791868743231 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868743317 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868743317 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1791868743927 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868743927 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791868743927 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791868743928 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1791868743928 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791868743928 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1791868743929 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1791868743934 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791868743935 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743936 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743939 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743940 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743941 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743942 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743942 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791868743945 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791868743995 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791868745087 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868745180 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791868745180 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791868745181 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791868745181 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745181 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745183 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745184 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745185 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745185 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745186 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791868745188 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791868745441 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791868746020 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868746061 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791868746061 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791868746061 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791868746062 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746063 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746063 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746064 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746065 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746066 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791868746068 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868746215 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791868746215 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791868746215 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791868746215 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746216 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746217 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746218 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746219 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746219 ""} -{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791868747876 ""} -{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791868747876 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "757 " "Peak virtual memory: 757 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868747905 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:19:07 2026 " "Processing ended: Tue Oct 13 16:19:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868747905 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868747905 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868747905 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1791868747905 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791870494616 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791870494617 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:48:14 2026 " "Processing started: Tue Oct 13 16:48:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791870494617 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1791870494617 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta assignment2 -c assignment2 " "Command: quartus_sta assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1791870494617 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1791870494671 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1791870495176 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870495246 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870495246 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1791870495827 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870495827 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791870495828 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791870495828 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1791870495828 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791870495829 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1791870495829 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1791870495834 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791870495834 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495835 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495839 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495840 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495840 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495841 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495842 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791870495844 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791870495888 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791870496882 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870496981 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791870496981 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791870496982 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791870496982 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496983 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496984 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496985 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496986 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496986 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496987 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791870496989 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791870497237 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791870497794 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870497852 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791870497852 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791870497852 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791870497853 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497854 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497856 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497857 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497858 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497859 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791870497862 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870498013 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791870498013 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791870498013 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791870498013 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498014 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498015 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498016 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498017 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498017 ""} +{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791870499645 ""} +{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791870499646 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "761 " "Peak virtual memory: 761 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791870499676 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:48:19 2026 " "Processing ended: Tue Oct 13 16:48:19 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791870499676 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791870499676 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791870499676 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1791870499676 ""} diff --git a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb index 3e6a483..19f4958 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb index c160595..fa9fc18 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb index f96ec8c..b14f66a 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb index 412a9a3..8ffeed4 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tmw_info b/Quartus/A2/db/assignment2.tmw_info index ae8044d..073d5c5 100644 --- a/Quartus/A2/db/assignment2.tmw_info +++ b/Quartus/A2/db/assignment2.tmw_info @@ -1,7 +1,7 @@ -start_full_compilation:s:00:01:00 +start_full_compilation:s:00:00:57 start_analysis_synthesis:s:00:00:12-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:32-start_full_compilation -start_assembler:s:00:00:07-start_full_compilation +start_fitter:s:00:00:30-start_full_compilation +start_assembler:s:00:00:06-start_full_compilation start_timing_analyzer:s:00:00:07-start_full_compilation start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/Quartus/A2/db/prev_cmp_assignment2.qmsg b/Quartus/A2/db/prev_cmp_assignment2.qmsg index 8596cc3..b440db2 100644 --- a/Quartus/A2/db/prev_cmp_assignment2.qmsg +++ b/Quartus/A2/db/prev_cmp_assignment2.qmsg @@ -1,57 +1,5 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868619871 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868619871 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:16:59 2026 " "Processing started: Tue Oct 13 16:16:59 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868619871 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868619871 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868619871 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791868620205 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791868620205 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 13 13 " "Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "11 seven_seg " "Found entity 11: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg_4digit " "Found entity 12: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "13 assignment2 " "Found entity 13: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868629731 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791868629879 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(54) " "Verilog HDL or VHDL warning at assignment2.sv(54): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 54 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791868629882 "|assignment2"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629883 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629891 ""} -{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791868629900 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868629925 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868629925 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868629925 "|assignment2|rom:ROM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629929 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 68 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629932 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 74 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629934 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 77 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629941 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629947 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629953 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" { } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629959 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_4digit seven_seg_4digit:display " "Elaborating entity \"seven_seg_4digit\" for hierarchy \"seven_seg_4digit:display\"" { } { { "../../modules/assignment2.sv" "display" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629964 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg_4digit:display\|seven_seg:digit0 " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg_4digit:display\|seven_seg:digit0\"" { } { { "../../modules/seven_seg_4digit.sv" "digit0" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629967 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630011 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630012 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630013 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630014 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630015 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791868630532 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[0\] GND " "Pin \"out_seg_0\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[1\] GND " "Pin \"out_seg_0\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[2\] GND " "Pin \"out_seg_0\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[3\] VCC " "Pin \"out_seg_0\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[4\] GND " "Pin \"out_seg_0\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[5\] GND " "Pin \"out_seg_0\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[6\] VCC " "Pin \"out_seg_0\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[7\] GND " "Pin \"out_seg_0\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[0\] GND " "Pin \"out_seg_1\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[1\] VCC " "Pin \"out_seg_1\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[2\] GND " "Pin \"out_seg_1\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[3\] GND " "Pin \"out_seg_1\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[4\] VCC " "Pin \"out_seg_1\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[5\] VCC " "Pin \"out_seg_1\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[6\] GND " "Pin \"out_seg_1\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[7\] GND " "Pin \"out_seg_1\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[0\] GND " "Pin \"out_seg_2\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[1\] GND " "Pin \"out_seg_2\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[2\] GND " "Pin \"out_seg_2\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[3\] GND " "Pin \"out_seg_2\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[4\] GND " "Pin \"out_seg_2\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[5\] VCC " "Pin \"out_seg_2\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[6\] VCC " "Pin \"out_seg_2\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[7\] GND " "Pin \"out_seg_2\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[0\] GND " "Pin \"out_seg_3\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[1\] GND " "Pin \"out_seg_3\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[2\] VCC " "Pin \"out_seg_3\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[3\] VCC " "Pin \"out_seg_3\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[4\] GND " "Pin \"out_seg_3\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[5\] GND " "Pin \"out_seg_3\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[6\] GND " "Pin \"out_seg_3\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[7\] VCC " "Pin \"out_seg_3\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630549 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791868630553 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791868630688 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868630688 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|clk[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[0\] " "No output dependent on input pin \"HID_Register\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[1\] " "No output dependent on input pin \"HID_Register\[1\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[2\] " "No output dependent on input pin \"HID_Register\[2\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[3\] " "No output dependent on input pin \"HID_Register\[3\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[4\] " "No output dependent on input pin \"HID_Register\[4\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_PC\[0\] " "No output dependent on input pin \"HID_PC\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_PC[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Hi_Low\[0\] " "No output dependent on input pin \"HID_Hi_Low\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Hi_Low[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791868630724 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791868630724 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791868630724 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791868630724 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 214 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "428 " "Peak virtual memory: 428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868630737 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:17:10 2026 " "Processing ended: Tue Oct 13 16:17:10 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868630737 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868630737 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868630737 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868630737 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1791868632250 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868632250 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:17:11 2026 " "Processing started: Tue Oct 13 16:17:11 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868632250 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1791868632250 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1791868632250 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1791868632306 ""} -{ "Info" "0" "" "Project = assignment2" { } { } 0 0 "Project = assignment2" 0 0 "Fitter" 0 0 1791868632307 ""} -{ "Info" "0" "" "Revision = assignment2" { } { } 0 0 "Revision = assignment2" 0 0 "Fitter" 0 0 1791868632307 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1791868632503 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1791868632503 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "assignment2 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"assignment2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1791868632508 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791868632575 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791868632575 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1791868632996 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1791868633024 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1791868633075 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 40 " "No exact pin location assignment(s) for 4 pins of 40 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1791868633333 ""} -{ "Error" "EFIOMGR_IO_BANK_OUTPUTS_VCCIO_INCOMPATIBLE" "out_seg_2\[7\] 5A 3.3-V LVTTL 3.3V 2.5V " "Pin out_seg_2\[7\] with I/O standard assignment 3.3-V LVTTL is incompatible with I/O bank 5A. I/O standard 3.3-V LVTTL, has a VCCIO requirement of 3.3V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 2.5V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 56 14177 15141 0 0 "" 0 "" "" } } } } } 0 169026 "Pin %1!s! with I/O standard assignment %3!s! is incompatible with I/O bank %2!s!. I/O standard %3!s!, has a VCCIO requirement of %4!s!, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of %5!s!. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Fitter" 0 -1 1791868633341 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868633342 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1791868633368 ""} -{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "32 " "Following 32 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[0\] GND " "Pin out_seg_0\[0\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[0] } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[1\] GND " "Pin out_seg_0\[1\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[1] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[1\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 34 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[2\] GND " "Pin out_seg_0\[2\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[2] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[2\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[3\] VCC " "Pin out_seg_0\[3\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[3] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[3\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 36 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[4\] GND " "Pin out_seg_0\[4\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[4] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[4\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 37 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[5\] GND " "Pin out_seg_0\[5\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[5] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[5\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 38 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[6\] VCC " "Pin out_seg_0\[6\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[6] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[6\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 39 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[7\] GND " "Pin out_seg_0\[7\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 40 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[0\] GND " "Pin out_seg_1\[0\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[0] } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 41 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[1\] VCC " "Pin out_seg_1\[1\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[1] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[1\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[2\] GND " "Pin out_seg_1\[2\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[2] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[2\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 43 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[3\] GND " "Pin out_seg_1\[3\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[3] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[3\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 44 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[4\] VCC " "Pin out_seg_1\[4\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[4] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[4\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 45 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[5\] VCC " "Pin out_seg_1\[5\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[5] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[5\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 46 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[6\] GND " "Pin out_seg_1\[6\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[6] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[6\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 47 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[7\] GND " "Pin out_seg_1\[7\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 48 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[0\] GND " "Pin out_seg_2\[0\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[0] } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 49 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[1\] GND " "Pin out_seg_2\[1\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[1] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[1\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 50 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[2\] GND " "Pin out_seg_2\[2\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[2] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[2\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 51 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[3\] GND " "Pin out_seg_2\[3\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[3] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[3\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 52 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[4\] GND " "Pin out_seg_2\[4\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[4] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[4\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 53 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[5\] VCC " "Pin out_seg_2\[5\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[5] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[5\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 54 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[6\] VCC " "Pin out_seg_2\[6\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[6] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[6\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 55 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[7\] GND " "Pin out_seg_2\[7\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 56 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[0\] GND " "Pin out_seg_3\[0\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[0] } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 57 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[1\] GND " "Pin out_seg_3\[1\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[1] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[1\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 58 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[2\] VCC " "Pin out_seg_3\[2\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[2] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[2\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 59 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[3\] VCC " "Pin out_seg_3\[3\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[3] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[3\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 60 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[4\] GND " "Pin out_seg_3\[4\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[4] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[4\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 61 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[5\] GND " "Pin out_seg_3\[5\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[5] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[5\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 62 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[6\] GND " "Pin out_seg_3\[6\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[6] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[6\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 63 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[7\] VCC " "Pin out_seg_3\[7\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 64 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} } { } 0 169069 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1791868633370 ""} -{ "Error" "EFSV_FITCC_FAIL" "" "Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { } 0 11802 "Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Fitter" 0 -1 1791868633372 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 6 s Quartus Prime " "Quartus Prime Fitter was unsuccessful. 2 errors, 6 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "514 " "Peak virtual memory: 514 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868633478 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 16:17:13 2026 " "Processing ended: Tue Oct 13 16:17:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868633478 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868633478 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868633478 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791868633478 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 220 s " "Quartus Prime Full Compilation was unsuccessful. 4 errors, 220 warnings" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791868634102 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791870416152 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791870416153 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:46:55 2026 " "Processing started: Tue Oct 13 16:46:55 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791870416153 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791870416153 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791870416153 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1791870416494 ""} +{ "Warning" "WQCU_PARALLEL_TOO_MANY_PROCESSORS" "4 2 " "Parallel compilation is enabled for 4 processors, but there are only 2 processors in the system. Runtime may increase due to over usage of the processor space." { } { } 0 20031 "Parallel compilation is enabled for %1!i! processors, but there are only %2!i! processors in the system. Runtime may increase due to over usage of the processor space." 0 0 "Analysis & Synthesis" 0 -1 1791870416494 ""} diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb index 4b00f12..7e782ee 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb index 4efd65e..e86afbf 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb index 2d041fa..ead12c0 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb index edf3be1..7077f1a 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb index ebf05aa..fc419c2 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi index 17630fb..a1d0bac 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb index 4e00665..5b624e0 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb index 3f83162..4b3a4b8 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb index 14196c3..aafd113 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb index 3cf1508..6b5bf26 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb differ diff --git a/Quartus/A2/output_files/assignment2.asm.rpt b/Quartus/A2/output_files/assignment2.asm.rpt index a28a8da..df3a6a1 100644 --- a/Quartus/A2/output_files/assignment2.asm.rpt +++ b/Quartus/A2/output_files/assignment2.asm.rpt @@ -1,5 +1,5 @@ Assembler report for assignment2 -Tue Oct 13 16:19:01 2026 +Tue Oct 13 16:48:13 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Oct 13 16:19:01 2026 ; +; Assembler Status ; Successful - Tue Oct 13 16:48:13 2026 ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; ; Family ; Cyclone V ; @@ -78,14 +78,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 16:18:55 2026 + Info: Processing started: Tue Oct 13 16:48:07 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files -Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 508 megabytes - Info: Processing ended: Tue Oct 13 16:19:01 2026 +Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 516 megabytes + Info: Processing ended: Tue Oct 13 16:48:13 2026 Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A2/output_files/assignment2.done b/Quartus/A2/output_files/assignment2.done index 35dfb65..e410369 100644 --- a/Quartus/A2/output_files/assignment2.done +++ b/Quartus/A2/output_files/assignment2.done @@ -1 +1 @@ -Tue Oct 13 16:19:11 2026 +Tue Oct 13 16:48:22 2026 diff --git a/Quartus/A2/output_files/assignment2.eda.rpt b/Quartus/A2/output_files/assignment2.eda.rpt index 4f23f94..b01099f 100644 --- a/Quartus/A2/output_files/assignment2.eda.rpt +++ b/Quartus/A2/output_files/assignment2.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for assignment2 -Tue Oct 13 16:19:10 2026 +Tue Oct 13 16:48:22 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:19:10 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:48:22 2026 ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; ; Family ; Cyclone V ; @@ -81,13 +81,12 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 16:19:09 2026 + Info: Processing started: Tue Oct 13 16:48:21 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool -Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 670 megabytes - Info: Processing ended: Tue Oct 13 16:19:10 2026 + Info: Processing ended: Tue Oct 13 16:48:22 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A2/output_files/assignment2.fit.rpt b/Quartus/A2/output_files/assignment2.fit.rpt index 784149d..69b0697 100644 --- a/Quartus/A2/output_files/assignment2.fit.rpt +++ b/Quartus/A2/output_files/assignment2.fit.rpt @@ -1,5 +1,5 @@ Fitter report for assignment2 -Tue Oct 13 16:18:53 2026 +Tue Oct 13 16:48:05 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -58,7 +58,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Oct 13 16:18:53 2026 ; +; Fitter Status ; Successful - Tue Oct 13 16:48:05 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; @@ -87,6 +87,7 @@ on the Quartus Prime software download page. ; Option ; Setting ; Default Value ; +--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ ; Device ; 5CGXFC5C6F27C7 ; ; +; Maximum processors allowed for parallel compilation ; 2 ; ; ; Minimum Core Junction Temperature ; 0 ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; Use smart compilation ; Off ; Off ; @@ -1422,8 +1423,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------+ ; Fitter Messages ; +-----------------+ -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (20032): Parallel compilation is enabled and will use up to 2 processors Info (119006): Selected device 5CGXFC5C6F27C7 for design "assignment2" Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C @@ -1446,7 +1446,7 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. Info (170189): Fitter placement preparation operations beginning Info (14951): The Fitter is using Advanced Physical Optimization. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 @@ -1457,17 +1457,17 @@ Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.06 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05 +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings - Info: Peak virtual memory: 1337 megabytes - Info: Processing ended: Tue Oct 13 16:18:53 2026 - Info: Elapsed time: 00:00:30 - Info: Total CPU time (on all processors): 00:00:42 +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 1328 megabytes + Info: Processing ended: Tue Oct 13 16:48:06 2026 + Info: Elapsed time: 00:00:28 + Info: Total CPU time (on all processors): 00:00:39 diff --git a/Quartus/A2/output_files/assignment2.fit.summary b/Quartus/A2/output_files/assignment2.fit.summary index 1a40484..eae105d 100644 --- a/Quartus/A2/output_files/assignment2.fit.summary +++ b/Quartus/A2/output_files/assignment2.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Oct 13 16:18:53 2026 +Fitter Status : Successful - Tue Oct 13 16:48:05 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : assignment2 Top-level Entity Name : assignment2 diff --git a/Quartus/A2/output_files/assignment2.flow.rpt b/Quartus/A2/output_files/assignment2.flow.rpt index 96db9f2..2a13ab6 100644 --- a/Quartus/A2/output_files/assignment2.flow.rpt +++ b/Quartus/A2/output_files/assignment2.flow.rpt @@ -1,5 +1,5 @@ Flow report for assignment2 -Tue Oct 13 16:19:10 2026 +Tue Oct 13 16:48:22 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,7 +41,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Oct 13 16:19:10 2026 ; +; Flow Status ; Successful - Tue Oct 13 16:48:22 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 10/13/2026 16:18:11 ; +; Start date & time ; 10/13/2026 16:47:27 ; ; Main task ; Compilation ; ; Revision Name ; assignment2 ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 117114050183607.179186869111054 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 117114050183607.179187044712686 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -89,6 +89,7 @@ on the Quartus Prime software download page. ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; NUM_PARALLEL_PROCESSORS ; 2 ; -- ; -- ; -- ; ; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; @@ -102,12 +103,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 410 MB ; 00:00:25 ; -; Fitter ; 00:00:30 ; 1.0 ; 1337 MB ; 00:00:42 ; -; Assembler ; 00:00:06 ; 1.0 ; 508 MB ; 00:00:06 ; -; Timing Analyzer ; 00:00:05 ; 1.0 ; 757 MB ; 00:00:05 ; +; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 412 MB ; 00:00:23 ; +; Fitter ; 00:00:27 ; 1.0 ; 1328 MB ; 00:00:38 ; +; Assembler ; 00:00:06 ; 1.0 ; 516 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:05 ; 1.0 ; 761 MB ; 00:00:05 ; ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ; -; Total ; 00:00:53 ; -- ; -- ; 00:01:19 ; +; Total ; 00:00:49 ; -- ; -- ; 00:01:12 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A2/output_files/assignment2.map.rpt b/Quartus/A2/output_files/assignment2.map.rpt index e960287..9d2ce4f 100644 --- a/Quartus/A2/output_files/assignment2.map.rpt +++ b/Quartus/A2/output_files/assignment2.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for assignment2 -Tue Oct 13 16:18:22 2026 +Tue Oct 13 16:47:37 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -63,7 +63,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Oct 13 16:18:22 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Oct 13 16:47:37 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; @@ -91,6 +91,7 @@ on the Quartus Prime software download page. ; Device ; 5CGXFC5C6F27C7 ; ; ; Top-level entity name ; assignment2 ; assignment2 ; ; Family name ; Cyclone V ; Cyclone V ; +; Maximum processors allowed for parallel compilation ; 2 ; ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; @@ -502,10 +503,9 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 16:18:11 2026 + Info: Processing started: Tue Oct 13 16:47:26 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (20032): Parallel compilation is enabled and will use up to 2 processors Info (12021): Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4 Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4 @@ -751,10 +751,10 @@ Warning (21074): Design contains 8 input pin(s) that do not drive logic Info (21057): Implemented 40 device resources after synthesis - the final resource count might be different Info (21058): Implemented 8 input pins Info (21059): Implemented 32 output pins -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings - Info: Peak virtual memory: 423 megabytes - Info: Processing ended: Tue Oct 13 16:18:22 2026 +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 213 warnings + Info: Peak virtual memory: 425 megabytes + Info: Processing ended: Tue Oct 13 16:47:37 2026 Info: Elapsed time: 00:00:11 - Info: Total CPU time (on all processors): 00:00:25 + Info: Total CPU time (on all processors): 00:00:23 diff --git a/Quartus/A2/output_files/assignment2.map.summary b/Quartus/A2/output_files/assignment2.map.summary index 0bfa021..dc5c712 100644 --- a/Quartus/A2/output_files/assignment2.map.summary +++ b/Quartus/A2/output_files/assignment2.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Tue Oct 13 16:18:22 2026 +Analysis & Synthesis Status : Successful - Tue Oct 13 16:47:37 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : assignment2 Top-level Entity Name : assignment2 diff --git a/Quartus/A2/output_files/assignment2.sta.rpt b/Quartus/A2/output_files/assignment2.sta.rpt index 10b7abf..40f363a 100644 --- a/Quartus/A2/output_files/assignment2.sta.rpt +++ b/Quartus/A2/output_files/assignment2.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for assignment2 -Tue Oct 13 16:19:07 2026 +Tue Oct 13 16:48:19 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -535,11 +535,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 16:19:02 2026 + Info: Processing started: Tue Oct 13 16:48:14 2026 Info: Command: quartus_sta assignment2 -c assignment2 Info: qsta_default_script.tcl version: #1 -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (20032): Parallel compilation is enabled and will use up to 2 processors Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Critical Warning (332012): Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. @@ -594,10 +593,10 @@ Info (332140): No Removal paths to report Info (332140): No Minimum Pulse Width paths to report Info (332101): Design is fully constrained for setup requirements Info (332101): Design is fully constrained for hold requirements -Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 757 megabytes - Info: Processing ended: Tue Oct 13 16:19:07 2026 +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 761 megabytes + Info: Processing ended: Tue Oct 13 16:48:19 2026 Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:06 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A2/simulation/questa/assignment2.svo b/Quartus/A2/simulation/questa/assignment2.svo index 14687a1..6e1640e 100644 --- a/Quartus/A2/simulation/questa/assignment2.svo +++ b/Quartus/A2/simulation/questa/assignment2.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "10/13/2026 16:19:10" +// DATE "10/13/2026 16:48:22" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672