TroubleElectrical/FPGA_Uni
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TODO: Remove Shifter Code

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TroubleElectrical committed 2026-10-13 16:57:03 +11:00
1 parent 25a953cdc6
commit 80416e1f8a
70 files changed
+213 -270
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Quartus/A2/output_files/assignment2.asm.rpt
+7 -8
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@@ -1,5 +1,5 @@
Assembler report for assignment2
Tue Oct 13 16:19:01 2026
Tue Oct 13 16:48:13 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Oct 13 16:19:01 2026 ;
; Assembler Status ; Successful - Tue Oct 13 16:48:13 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
@@ -78,14 +78,13 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:18:55 2026
Info: Processing started: Tue Oct 13 16:48:07 2026
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 508 megabytes
Info: Processing ended: Tue Oct 13 16:19:01 2026
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 516 megabytes
Info: Processing ended: Tue Oct 13 16:48:13 2026
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:06
Info: Total CPU time (on all processors): 00:00:05
Quartus/A2/output_files/assignment2.done
+1 -1
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@@ -1 +1 @@
Tue Oct 13 16:19:11 2026
Tue Oct 13 16:48:22 2026
Quartus/A2/output_files/assignment2.eda.rpt
+5 -6
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@@ -1,5 +1,5 @@
EDA Netlist Writer report for assignment2
Tue Oct 13 16:19:10 2026
Tue Oct 13 16:48:22 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:19:10 2026 ;
; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:48:22 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
@@ -81,13 +81,12 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:19:09 2026
Info: Processing started: Tue Oct 13 16:48:21 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 670 megabytes
Info: Processing ended: Tue Oct 13 16:19:10 2026
Info: Processing ended: Tue Oct 13 16:48:22 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Quartus/A2/output_files/assignment2.fit.rpt
+12 -12
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@@ -1,5 +1,5 @@
Fitter report for assignment2
Tue Oct 13 16:18:53 2026
Tue Oct 13 16:48:05 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -58,7 +58,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Tue Oct 13 16:18:53 2026 ;
; Fitter Status ; Successful - Tue Oct 13 16:48:05 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
@@ -87,6 +87,7 @@ on the Quartus Prime software download page.
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device ; 5CGXFC5C6F27C7 ; ;
; Maximum processors allowed for parallel compilation ; 2 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Use smart compilation ; Off ; Off ;
@@ -1422,8 +1423,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------+
; Fitter Messages ;
+-----------------+
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (20032): Parallel compilation is enabled and will use up to 2 processors
Info (119006): Selected device 5CGXFC5C6F27C7 for design "assignment2"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
@@ -1446,7 +1446,7 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (170189): Fitter placement preparation operations beginning
Info (14951): The Fitter is using Advanced Physical Optimization.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
@@ -1457,17 +1457,17 @@ Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.06 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings
Info: Peak virtual memory: 1337 megabytes
Info: Processing ended: Tue Oct 13 16:18:53 2026
Info: Elapsed time: 00:00:30
Info: Total CPU time (on all processors): 00:00:42
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 1328 megabytes
Info: Processing ended: Tue Oct 13 16:48:06 2026
Info: Elapsed time: 00:00:28
Info: Total CPU time (on all processors): 00:00:39
Quartus/A2/output_files/assignment2.fit.summary
+1 -1
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@@ -1,4 +1,4 @@
Fitter Status : Successful - Tue Oct 13 16:18:53 2026
Fitter Status : Successful - Tue Oct 13 16:48:05 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Quartus/A2/output_files/assignment2.flow.rpt
+10 -9
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@@ -1,5 +1,5 @@
Flow report for assignment2
Tue Oct 13 16:19:10 2026
Tue Oct 13 16:48:22 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Oct 13 16:19:10 2026 ;
; Flow Status ; Successful - Tue Oct 13 16:48:22 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/13/2026 16:18:11 ;
; Start date & time ; 10/13/2026 16:47:27 ;
; Main task ; Compilation ;
; Revision Name ; assignment2 ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 117114050183607.179186869111054 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 117114050183607.179187044712686 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -89,6 +89,7 @@ on the Quartus Prime software download page.
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 2 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
@@ -102,12 +103,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 410 MB ; 00:00:25 ;
; Fitter ; 00:00:30 ; 1.0 ; 1337 MB ; 00:00:42 ;
; Assembler ; 00:00:06 ; 1.0 ; 508 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 757 MB ; 00:00:05 ;
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 412 MB ; 00:00:23 ;
; Fitter ; 00:00:27 ; 1.0 ; 1328 MB ; 00:00:38 ;
; Assembler ; 00:00:06 ; 1.0 ; 516 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 761 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
; Total ; 00:00:53 ; -- ; -- ; 00:01:19 ;
; Total ; 00:00:49 ; -- ; -- ; 00:01:12 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
Quartus/A2/output_files/assignment2.map.rpt
+9 -9
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for assignment2
Tue Oct 13 16:18:22 2026
Tue Oct 13 16:47:37 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -63,7 +63,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Oct 13 16:18:22 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Oct 13 16:47:37 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
@@ -91,6 +91,7 @@ on the Quartus Prime software download page.
; Device ; 5CGXFC5C6F27C7 ; ;
; Top-level entity name ; assignment2 ; assignment2 ;
; Family name ; Cyclone V ; Cyclone V ;
; Maximum processors allowed for parallel compilation ; 2 ; ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
@@ -502,10 +503,9 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:18:11 2026
Info: Processing started: Tue Oct 13 16:47:26 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (20032): Parallel compilation is enabled and will use up to 2 processors
Info (12021): Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4
Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4
@@ -751,10 +751,10 @@ Warning (21074): Design contains 8 input pin(s) that do not drive logic
Info (21057): Implemented 40 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 8 input pins
Info (21059): Implemented 32 output pins
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings
Info: Peak virtual memory: 423 megabytes
Info: Processing ended: Tue Oct 13 16:18:22 2026
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 213 warnings
Info: Peak virtual memory: 425 megabytes
Info: Processing ended: Tue Oct 13 16:47:37 2026
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:25
Info: Total CPU time (on all processors): 00:00:23
Quartus/A2/output_files/assignment2.map.summary
+1 -1
View File
@@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Tue Oct 13 16:18:22 2026
Analysis & Synthesis Status : Successful - Tue Oct 13 16:47:37 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Quartus/A2/output_files/assignment2.sta.rpt
+7 -8
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@@ -1,5 +1,5 @@
Timing Analyzer report for assignment2
Tue Oct 13 16:19:07 2026
Tue Oct 13 16:48:19 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -535,11 +535,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:19:02 2026
Info: Processing started: Tue Oct 13 16:48:14 2026
Info: Command: quartus_sta assignment2 -c assignment2
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (20032): Parallel compilation is enabled and will use up to 2 processors
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
@@ -594,10 +593,10 @@ Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332101): Design is fully constrained for setup requirements
Info (332101): Design is fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 757 megabytes
Info: Processing ended: Tue Oct 13 16:19:07 2026
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 761 megabytes
Info: Processing ended: Tue Oct 13 16:48:19 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:06
Info: Total CPU time (on all processors): 00:00:05