TroubleElectrical/FPGA_Uni
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Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output

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riley committed 2026-09-13 23:08:07 +10:00
1 parent f69f87ccab
commit 78efccfe1e
3 files changed
+207 -23
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modules/alu.sv
+18 -13
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@@ -1,3 +1,6 @@
`ifndef ALU_H_SV
`define ALU_H_SV
`include "asu.sv"
`include "lu.sv"
@@ -5,8 +8,9 @@
// flags[1:1] = Overflow
module alu #(parameter width=2)(input logic [3:0] op,
input logic [2**width-1:0] A, input logic [2**width-1:0] B,
output logic [2**width-1:0] OUT_1, output logic flags[1:0]);
output logic [2**width-1:0] OUT_1, output logic[1:0] flags);
logic [0:0] asu_op;
logic [2**width-1:0] asu_out;
logic [1:0] asu_flags;
asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
@@ -16,17 +20,18 @@ module alu #(parameter width=2)(input logic [3:0] op,
always_comb begin
case (op)
2'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
2'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
2'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
2'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
2'b0100: OUT_1 = lu_out;
2'b0101: OUT_1 = lu_out;
2'b0110: OUT_1 = lu_out;
2'b0111: OUT_1 = lu_out;
2'b1010: OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]);
2'b1011: OUT_1 = ~asu_flags[0];
default: '0;
4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0100: OUT_1 = lu_out;
4'b0101: OUT_1 = lu_out;
4'b0110: OUT_1 = lu_out;
4'b0111: OUT_1 = lu_out;
4'b1010: OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1};
4'b1011: OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1};
default: OUT_1 = {(2**width){1'b0}};
endcase
end
endmodule
endmodule
`endif