TroubleElectrical/FPGA_Uni
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Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.

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riley committed 2026-11-05 14:27:01 +11:00
1 parent 00b2087860
commit 74a15cf038
3 files changed
+13 -12
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modules/assignment3.sv
+4 -4
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@@ -42,7 +42,7 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
logic [2**width-1:0] rom_rd;
logic [2**width-1:0] rom_addr;
logic [2**width-1:0] instruction, instruction_1;
rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
rom #("./asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex", romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr);
gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);
@@ -90,10 +90,10 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
logic [3:0] alu_flags, alu_flags_1;
alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags);
alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags[2:0]);
gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
gatereg #(2, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
assign rd_alu = alu_out_2;
logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
@@ -104,7 +104,7 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
assign pc_addr_write = new_pc_addr_1;
assign pc_we = B & alu_flags_1[2];
logic [2**width-1:0] mem_out, mem_out_1;
ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out);
ram #(ramsz, width) RAM (clk, rst, alu_out_1[ramsz-1:0], MEM_WE, regf_rt_2, mem_out);
gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
assign rd_mem = mem_out_1;
endmodule