TroubleElectrical/FPGA_Uni
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Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.

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riley committed 2026-11-05 14:27:01 +11:00
1 parent 00b2087860
commit 74a15cf038
3 files changed
+13 -12
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modules/assignment2.sv
+7 -2
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@@ -58,10 +58,15 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
rom #(romsz, width) ROM (pc_addr, instruction);
`ifdef QUARTUS_SYNTH
rom #("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", romsz, width) ROM (pc_addr[romsz-1:0], instruction);
`else
rom #("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", romsz, width) ROM (pc_addr[romsz-1:0], instruction);
`endif
logic [2**width-1:0] rd_mem;
ram #(ramsz, width) RAM (clk, rst, rd_alu, M2W, rt, rd_mem);
ram #(ramsz, width) RAM (clk, rst, rd_alu[ramsz-1:0], M2W, rt, rd_mem);
control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW