Renamed MIPS test to be a single cycle test

tests/mips_singlecycle.sv

@@ -13,7 +13,7 @@
         num_errors += 1;                                  \
     end
 
-module mips_tb();
+module mips_single_cycle_tb();
     logic [0:0] clk;
     logic [0:0] rst;
     assignment2 #(5) CPU (clk, rst);
@@ -42,7 +42,7 @@ module mips_tb();
         $dumpvars(7, CPU.rt_imm);
 
         // Zero out lower registers
-        $display("Beginning MIPS tests");
+        $display("Beginning Single-cycle MIPS tests");
 
         // Check R-type / initialise
         #2;
@@ -119,8 +119,8 @@ module mips_tb();
         `TEST_CHECK(CPU.REGS.regs[22] == 32'd0);
         `TEST_CHECK(CPU.REGS.regs[23] == 32'd0);
 
-        if (num_errors == 0) begin $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m");
-        end else begin $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors); end
+        if (num_errors == 0) begin $display("\x1b[38;5;10mAll Single-cycle MIPS tests passing\x1b[m");
+        end else begin $display("\x1b[38;5;9m%0d Single-cycle MIPS test(s) failing\x1b[m", num_errors); end
 
         $dumpflush;
         $finish;

tests/tests.sv

@@ -4,4 +4,4 @@
 `include "tests/instruction_classifier_tb.sv"
 `include "tests/shifter_tb.sv"
 `include "tests/alu_tb.sv"
-`include "tests/mips.sv"
+`include "tests/mips_singlecycle.sv"