From 704286f0e6b0946ad9bd3543f572deda3e007030 Mon Sep 17 00:00:00 2001 From: Riley King-Saunders Date: Wed, 4 Nov 2026 15:42:52 +1100 Subject: [PATCH] Renamed MIPS test to be a single cycle test --- tests/{mips.sv => mips_singlecycle.sv} | 8 ++++---- tests/tests.sv | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) rename tests/{mips.sv => mips_singlecycle.sv} (93%) diff --git a/tests/mips.sv b/tests/mips_singlecycle.sv similarity index 93% rename from tests/mips.sv rename to tests/mips_singlecycle.sv index f070b44..51d9aaf 100644 --- a/tests/mips.sv +++ b/tests/mips_singlecycle.sv @@ -13,7 +13,7 @@ num_errors += 1; \ end -module mips_tb(); +module mips_single_cycle_tb(); logic [0:0] clk; logic [0:0] rst; assignment2 #(5) CPU (clk, rst); @@ -42,7 +42,7 @@ module mips_tb(); $dumpvars(7, CPU.rt_imm); // Zero out lower registers - $display("Beginning MIPS tests"); + $display("Beginning Single-cycle MIPS tests"); // Check R-type / initialise #2; @@ -119,8 +119,8 @@ module mips_tb(); `TEST_CHECK(CPU.REGS.regs[22] == 32'd0); `TEST_CHECK(CPU.REGS.regs[23] == 32'd0); - if (num_errors == 0) begin $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m"); - end else begin $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors); end + if (num_errors == 0) begin $display("\x1b[38;5;10mAll Single-cycle MIPS tests passing\x1b[m"); + end else begin $display("\x1b[38;5;9m%0d Single-cycle MIPS test(s) failing\x1b[m", num_errors); end $dumpflush; $finish; diff --git a/tests/tests.sv b/tests/tests.sv index 48fa8ed..49bde88 100644 --- a/tests/tests.sv +++ b/tests/tests.sv @@ -4,4 +4,4 @@ `include "tests/instruction_classifier_tb.sv" `include "tests/shifter_tb.sv" `include "tests/alu_tb.sv" -`include "tests/mips.sv" \ No newline at end of file +`include "tests/mips_singlecycle.sv" \ No newline at end of file