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Renamed MIPS test to be a single cycle test

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riley committed 2026-11-04 15:42:52 +11:00
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commit 704286f0e6
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tests/mips_singlecycle.sv
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`include "assignment2.sv"
`timescale 1us/10ns
`define PRINT_REGISTERS(regs)\
$display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",\
regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15], \
regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23] \
);
`define TEST_CHECK(cond) if (cond) begin end else begin \
$display("Check %s failed", `"cond`"); \
`PRINT_REGISTERS(CPU.REGS.regs); \
num_errors += 1; \
end
module mips_single_cycle_tb();
logic [0:0] clk;
logic [0:0] rst;
assignment2 #(5) CPU (clk, rst);
initial clk = 0;
initial rst = 0;
always #1 clk = ~clk;
integer num_errors = 0;
initial begin
rst = 1;
#2;
rst = 0;
#2;
$dumpfile("output.vcd");
$dumpvars(0, clk);
$dumpvars(1, CPU.REGS);
$dumpvars(2, CPU.ROM);
$dumpvars(3, CPU.PC);
$dumpvars(4, CPU.pc_addr);
$dumpvars(5, CPU.CONTROL_UNIT);
$dumpvars(5, CPU.instruction);
$dumpvars(5, CPU.ALU);
$dumpvars(6, CPU.flags);
$dumpvars(7, CPU.rt_imm);
// Zero out lower registers
$display("Beginning Single-cycle MIPS tests");
// Check R-type / initialise
#2;
`TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7));
// Check load-store
#2;
`TEST_CHECK(CPU.RAM.mem[0] == CPU.REGS.regs[9]);
#2;
`TEST_CHECK(CPU.REGS.regs[10] == CPU.RAM.mem[0]);
// Check arithmetic
#2;
`TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[9] + CPU.REGS.regs[10]));
#2;
`TEST_CHECK(CPU.REGS.regs[12] == (CPU.REGS.regs[9] - CPU.REGS.regs[11]));
#2;
`TEST_CHECK(CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3));
#2;
`TEST_CHECK(CPU.REGS.regs[14] == (CPU.REGS.regs[12] + CPU.REGS.regs[13]));
// Check logic instructions
#2;
`TEST_CHECK(CPU.REGS.regs[16] == (CPU.REGS.regs[9] & CPU.REGS.regs[13]));
#2;
`TEST_CHECK(CPU.REGS.regs[17] == (CPU.REGS.regs[9] | CPU.REGS.regs[13]));
#2;
`TEST_CHECK(CPU.REGS.regs[18] == (CPU.REGS.regs[9] ^ CPU.REGS.regs[13]));
#2;
`TEST_CHECK(CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ));
// Check SLT instructions
#2;
`TEST_CHECK(CPU.REGS.regs[20] == $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]));
#2;
`TEST_CHECK(CPU.REGS.regs[21] == $unsigned(CPU.REGS.regs[12]) < $unsigned(CPU.REGS.regs[14]));
// Check loop branching
#2;
for (integer N = 1; N < 11; ++N) begin
#2;
`TEST_CHECK(CPU.REGS.regs[8] == 32'(N));
#2;
`TEST_CHECK(CPU.REGS.regs[22] == $unsigned(CPU.REGS.regs[8]) < $unsigned(CPU.REGS.regs[13]));
if (N < 10)
#2;
#2;
end
// Final state check
#2;
#2;
#2;
#2;
#2;
`TEST_CHECK(CPU.REGS.regs[8] == 32'd10);
`TEST_CHECK(CPU.REGS.regs[9] == 32'd7);
`TEST_CHECK(CPU.REGS.regs[10] == 32'd7);
`TEST_CHECK(CPU.REGS.regs[11] == 32'd14);
`TEST_CHECK(CPU.REGS.regs[12] == -32'sd7);
`TEST_CHECK(CPU.REGS.regs[13] == 32'd10);
`TEST_CHECK(CPU.REGS.regs[14] == 32'd3);
`TEST_CHECK(CPU.REGS.regs[15] == 32'd0);
`TEST_CHECK(CPU.REGS.regs[16] == 32'd2);
`TEST_CHECK(CPU.REGS.regs[17] == 32'd15);
`TEST_CHECK(CPU.REGS.regs[18] == 32'd13);
`TEST_CHECK(CPU.REGS.regs[19] == -32'sd16);
`TEST_CHECK(CPU.REGS.regs[20] == 32'd1);
`TEST_CHECK(CPU.REGS.regs[21] == 32'd0);
`TEST_CHECK(CPU.REGS.regs[22] == 32'd0);
`TEST_CHECK(CPU.REGS.regs[23] == 32'd0);
if (num_errors == 0) begin $display("\x1b[38;5;10mAll Single-cycle MIPS tests passing\x1b[m");
end else begin $display("\x1b[38;5;9m%0d Single-cycle MIPS test(s) failing\x1b[m", num_errors); end
$dumpflush;
$finish;
end
endmodule