Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/assignment2.sv

@@ -1,11 +1,26 @@
-`include "rom.sv"
-`include "ram.sv"
-`include "register_file.sv"
-`include "instruction_counter.sv"
-`include "instruction_classifier.sv"
-`include "instruction_module_classifier.sv"
-`include "alu.sv"
-`include "shifter.sv"
+`ifndef ASS_2_SV
+`define ASS_2_SV
+
+`ifdef SYNTHESIS
+	`include "../../rom.sv"
+    `include "../../ram.sv"
+    `include "../../register_file.sv"
+    `include "../../instruction_counter.sv"
+    `include "../../instruction_classifier.sv"
+    `include "../../instruction_module_classifier.sv"
+    `include "../../alu.sv"
+    `include "../../shifter.sv"
+`else
+	`include "rom.sv"
+    `include "ram.sv"
+    `include "register_file.sv"
+    `include "instruction_counter.sv"
+    `include "instruction_classifier.sv"
+    `include "instruction_module_classifier.sv"
+    `include "alu.sv"
+    `include "shifter.sv"
+`endif
+
 
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
@@ -50,4 +65,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
     logic [2**width-1:0] rd_shifter;
     shifter SHIFTER #(width)(instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
     
-endmodule
+endmodule
+
+`endif