From 8675f5b8ee727ca6d40561ac07853fece54147e3 Mon Sep 17 00:00:00 2001 From: TroubleElectrical Date: Tue, 13 Oct 2026 12:03:55 +1100 Subject: [PATCH 1/2] Made Assignment 2 Quartus Project --- Quartus/A2/assignment2.qpf | 31 ++++++++++ Quartus/A2/assignment2.qsf | 57 +++++++++++++++++++ Quartus/A2/db/assignment2.db_info | 3 + .../A2/db/assignment2.quiproj.2400.rdr.flock | 0 4 files changed, 91 insertions(+) create mode 100644 Quartus/A2/assignment2.qpf create mode 100644 Quartus/A2/assignment2.qsf create mode 100644 Quartus/A2/db/assignment2.db_info create mode 100644 Quartus/A2/db/assignment2.quiproj.2400.rdr.flock diff --git a/Quartus/A2/assignment2.qpf b/Quartus/A2/assignment2.qpf new file mode 100644 index 0000000..581c063 --- /dev/null +++ b/Quartus/A2/assignment2.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 12:03:16 October 13, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "12:03:16 October 13, 2026" + +# Revisions + +PROJECT_REVISION = "assignment2" diff --git a/Quartus/A2/assignment2.qsf b/Quartus/A2/assignment2.qsf new file mode 100644 index 0000000..90ea31b --- /dev/null +++ b/Quartus/A2/assignment2.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 12:03:16 October 13, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# assignment2_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY assignment2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:03:16 OCTOBER 13, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/assignment2.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A2/db/assignment2.db_info b/Quartus/A2/db/assignment2.db_info new file mode 100644 index 0000000..d4bd959 --- /dev/null +++ b/Quartus/A2/db/assignment2.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Tue Oct 13 12:03:19 2026 diff --git a/Quartus/A2/db/assignment2.quiproj.2400.rdr.flock b/Quartus/A2/db/assignment2.quiproj.2400.rdr.flock new file mode 100644 index 0000000..e69de29 From e57e8f362a6a4e3a088e7eb2b5d35f0cfc0410f8 Mon Sep 17 00:00:00 2001 From: TroubleElectrical Date: Tue, 13 Oct 2026 12:23:52 +1100 Subject: [PATCH 2/2] Updated assignment 2 dependency modules (currently 8 errors in compile) --- Quartus/A2/assignment2.qsf | 6 +- Quartus/A2/db/assignment2.cmp.rdb | Bin 0 -> 4306 bytes Quartus/A2/db/assignment2.map.qmsg | 15 ++ Quartus/A2/db/assignment2.map.rdb | Bin 0 -> 1151 bytes Quartus/A2/db/assignment2.map_bb.hdb | Bin 0 -> 9924 bytes .../A2/db/assignment2.sld_design_entry.sci | Bin 0 -> 229 bytes Quartus/A2/db/assignment2.smart_action.txt | 1 + Quartus/A2/db/assignment2.tis_db_list.ddb | Bin 0 -> 242 bytes Quartus/A2/db/prev_cmp_assignment2.qmsg | 22 +++ Quartus/A2/output_files/assignment2.flow.rpt | 119 ++++++++++++ Quartus/A2/output_files/assignment2.map.rpt | 183 ++++++++++++++++++ .../A2/output_files/assignment2.map.summary | 12 ++ modules/assignment2.sv | 26 ++- modules/assignment2.sv.bak | 19 ++ modules/instruction_counter.sv | 8 +- modules/ram.sv | 11 +- modules/rom.sv | 4 + 17 files changed, 412 insertions(+), 14 deletions(-) create mode 100644 Quartus/A2/db/assignment2.cmp.rdb create mode 100644 Quartus/A2/db/assignment2.map.qmsg create mode 100644 Quartus/A2/db/assignment2.map.rdb create mode 100644 Quartus/A2/db/assignment2.map_bb.hdb create mode 100644 Quartus/A2/db/assignment2.sld_design_entry.sci create mode 100644 Quartus/A2/db/assignment2.smart_action.txt create mode 100644 Quartus/A2/db/assignment2.tis_db_list.ddb create mode 100644 Quartus/A2/db/prev_cmp_assignment2.qmsg create mode 100644 Quartus/A2/output_files/assignment2.flow.rpt create mode 100644 Quartus/A2/output_files/assignment2.map.rpt create mode 100644 Quartus/A2/output_files/assignment2.map.summary create mode 100644 modules/assignment2.sv.bak diff --git a/Quartus/A2/assignment2.qsf b/Quartus/A2/assignment2.qsf index 90ea31b..d08adfc 100644 --- a/Quartus/A2/assignment2.qsf +++ b/Quartus/A2/assignment2.qsf @@ -54,4 +54,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/A2/db/assignment2.cmp.rdb b/Quartus/A2/db/assignment2.cmp.rdb new file mode 100644 index 0000000000000000000000000000000000000000..3d32a8ead8786747bd603863e16506a295208be2 GIT binary patch literal 4306 zcmV;@5H0T%000233jqKC0001Q0B-;|00011WpZ|6PB8@Cmf+N5pNv`v%VC#H5{XKKnMZOO+pomrEV%nT{g zB<0xCA2=%#q_$q}GJ8l?{`vO%0PJ!hk-F++CLQgFB7g-R9v&Xvg~#{S*4946=STSP zSzllK7+%5okce|5py?60`$?tH}diKRA=@G(`23|V&eHS7LzEPsc}FGu*D>d z`erwL&&HFWQ4oJ0!< z1|aT6KRt*?kvCUd<4hwdIr%*W&y0DIf=FpBx{)`N`N&1z4N}7NZFZM*;Og~OxbwO1 zjobrY3VaiT4RyUdGwljniNFIO~gsY79MsZjMUt52zc`p9HrT%NO--m zdPib0bAxo^j*>J2r4LRv4A$fZ0AW+M5E4ECF;n0XdEanjyf}%xgER@FcvFb3FI}J? z$qCrUY=8mR&loPF@^T`BNpVt1Je$HfzmCJ>zz^LqxO6Hvd0Y#}aK{giML(U*+~{QK z8ARjy&-sso%I5REsVH#+r1|^@Prmk_p+T=*CJByKthy}uw@&GIo%NoEWr!}&t|s0K zgHl~i+|*CRt{)yi8ul;3oME;OEjwOZ20ax#`zvV zx>+3ym33&dce#HB(5h%~B9|zfI{gcewiO=k?Z@?hXtBj%V=Kutbc&!?`pZ$ zJg3ny3-~kIm+p1OW9O2C%P$^+H zLDX#xB$rGTtnUXQ_wiR;5yXA}Zzk)yjPpjP2LJ4T%&D z9V^rWDJgmgU=ozrb2FcqI2VjZ-Iq8F!gE0R72#UpwA%6Ky3-%wTnc@50Ft=4sh z)vq#)JKs^UXpLaO)zb~U=jbQc9x+C=9I=5UkJ``|0drR#kh!@|AMpfTLp->VIpojs>D+-nS4&Hg|Gpr_fHOmt-xWHO)} zyTgOfjmATLVKc;z;l%2J0$=ZLy1y=)?jTHqF=FJyc;p7(#;lA=oLMA;T&_R#f<#Uc z3Nx}!pzFI^?o#T;C$odlNWR~i={oy^?*3p{cLvUIr_*aYW)Ib2I)Nmc9m&YUO^J9u zHbYnKC`B%y7`@wA8z`TljjB$~bYe+m)T}t|RXD)!a~9 zoZARuN`QYL!Y==*$DW4>Cmb}}jbXp$v>Lkq`}nGexsg=ojb644QmpN~8rC{EU|$;6 z9}XJr?gE>~TZ{5V$4S9!?yZEE1vmh46{^K{N}R6K8#EPxYn@i7r*XN1uTn|e#jPxE z1?Rl`g$aTCF~~b8FjY}H*HF0#v{>e;hC$0OI3?i=ya*amH--u25{ z_|mGs*4a@y|b5TSYTJdBedw^?aD;3j23X=+zAScWns zT25b)oXjN}@SIN-5#IZf1^<9*=EgO+G3I^oeKF>F4Dyp@6f#+VFP$C8NVEPQ^E$F-5*WTvTaZ&T zeV%n6DoJxvr~upUTV&E84aY|YL?#T`$DFR*&0brSC}J~Viku=NL6xnrSvHc4eKOdK zJ_Ky+=LNV$=@Y!(=Zzv$NAks@5f7!+r&{(dq&8O|@Z^1kflkU)%H_@SrzqfI{ajaQ zgwIvZ;SY##bz_4q3Z{@huB}O|ErNLnorqe?e3CZ$NL_G}dB%+2ZY&FX{2;WAB z8m{xNuz`CD(y@;VQgaVcy?&+~0w46Eg`Id_M~DK1%&Zb~)^o4d-fX)@fzo#;Qdl7LWEQ2Z3O(P(Td)V%G+Vp{ z-~!q!ZqLSZ-B%e*%cMCCz#jSBUV!i!!d1wb&}YERZy{|}{!SoF4OO8JmG-Cn7X`r$ z7R&O(F!Sz6xvg?0zwO%n74QNiZ=DB|NL9CtO0X(SB;a}MLM-N|O$Qc{{?`nU2gt0# zp3}a7*gPYuyXvcRN_+0HP_Xb0Pf-#T%jAwcgCS3gQA1Xap{ZK$cf~Um1AONCZZNtu zEADj$Vwb$!P2o&D%TZ~6en$EfS5ho9b)X05rBr^~PmKQt6qI zyRFVMr*+wZif{Be>vg^oR~uYdXRFp|U3yY-kHNOz*%{cl771A_QyjIJxhotB6H4_d zXv%Ar2UYPbk3UcB#)U2Etb7xz4SfKh4@va@Z2>rHX zFij58h=x!AR$FPvf)_sTNR2WMFp6x$gu~+{-H~o8SQwizE`p`0b@hI%wgYggHi{-7dbP(MI)<137nmlOv_|O!xD|bK)?fh@Dz%-QC0R1q<=wM z)wQ4O{yJUwiy54-Ml}zV3PNsFbKjXF7RVsOxqOlHO2@x9=wSak@@{ndKrc zWUhs4Pm=#m=P6sHvMNsiQipITZ?xS7vo|xhP~xrvAoO5P0Mn|GrubcDx0A#R=>20k zPmCM-zrlTK!EFXdQsHtYm0yh3}a306w5Pw^T-hf*6qFQX9vd7K?Q>sV?i z)^e;0<;t>)5M+Ui3MwiIf3UH3LGL7odMNLPbt1mQ|iMxQ@Rl94U#f(&6(xJ%6+!HM3(N!>HYZi8oD+ z(@wiSK?rFkveX2Nx~B4900030|9Ao7VPIqsU|?Wq`e>ue2&9>Sm>YAgK^TZ(^8QXiSN*XL?fLHa>h42VJc{anN2-TZxAT!Z2v zN?E{4A3b~D#0*s`1XYTnj1{cxDuZG+$Tc7n1)<7(T-_agpoXzA>;Q`9ar}~isgi`M z3J&%4bqtD(4{>zzafPa8XV?Ig-72W4%mSoAW{N^pgItNMk^^izXHaS!%s-&;0r@Ay zH6jFR94A;&+VoAKFrSD(6}kF4xw^Qxx)Rco-Cb(lR0WM;8K>fSd>OGDKN$NRX$WdpuM%00030|Lu4_ AWdHyG literal 0 HcmV?d00001 diff --git a/Quartus/A2/db/assignment2.map.qmsg b/Quartus/A2/db/assignment2.map.qmsg new file mode 100644 index 0000000..b754c22 --- /dev/null +++ b/Quartus/A2/db/assignment2.map.qmsg @@ -0,0 +1,15 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791854502822 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791854502823 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 12:21:42 2026 " "Processing started: Tue Oct 13 12:21:42 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791854502823 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854502823 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854502823 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791854503126 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791854503126 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_we assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_we\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_addr assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_addr\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \")\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(27) " "Verilog HDL syntax error at assignment2.sv(27) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 27 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(28) " "Verilog HDL syntax error at assignment2.sv(28) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(29) " "Verilog HDL syntax error at assignment2.sv(29) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 29 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(20) " "Ignored design unit \"assignment2\" at assignment2.sv(20) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 20 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854512634 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 8 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 12:21:52 2026 " "Processing ended: Tue Oct 13 12:21:52 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854512678 ""} diff --git a/Quartus/A2/db/assignment2.map.rdb b/Quartus/A2/db/assignment2.map.rdb new file mode 100644 index 0000000000000000000000000000000000000000..676973dc2dcfc63d4cb153953db3952857d2dc38 GIT binary patch literal 1151 zcmV-_1c3V#000233jqKC0001Q0B-;|00011WpZA8#ffS(~`h6lt4l#p%0fnq*>T_*HgBTyt(c!6r7C{ zFM&Q4c}AX9s*gb*yPf>`_T16f+Z2~>^Av%QMsv^A(b2j3ax@yx}SMF;d-3^OZq7gV69wCZfUlssQ0V}$SUdv6;vg+3u+!u>P* z=uZb)-2OxxjrjC9F%w_NMrb;BQB{%y_O4cAjxg^fW8k@L+Zv-bWVpu(ymbzZIZ1xXP`pZ znjG%KQ*fJjExaUN8p3%hY)7r|(IO_piyi*359SD$Vw)mul$L=u-kBZ;Qpimk=VjxR zZK!yrY^77p^IBd(8*064yfB8B9B3$$bbsQU?BHgPLWJNdC8DgUc2zRc#vBQpve?Ds zPdGJ`_g?736$kgip{ zgz|_oDoeqXM5JzO3zQjj>Guu}`Pu|WWxM=c_@!@zkZ!d#+*alNBEzK6oW=WC;hkS= zcWt#3HC)=rNip75+P}X$kSc{7_8o>Z0oT^_oGy~2*Ko@82bz{I%jwILlI!uu9Qqi; z#}wX4A7F_5`xrxcGMR>0PmbxQq#)FETE3v^@liQF>g#$n$Gt~Mr`dKH_%(*Ns0B_% z=fVun1wSG%Jc^gCR_0jdaN*kLT3$&_r#7nC{TJpQFlWLjJ-oF1l+U|LJ1gm3PRmj) z`llg9rPYUAMyOSqEnbC#9P|Xk`O%CLcGa|m+xyy~SJF2FXMXuFT*SkNf`<{H&#kdv z?Xaz~w}(C4!LAhQ4_p5)_%}QFTD$6ZGSWET(HgG)1m?@d;!|Kh-wyT{00030|9Ao7 zWME_vU|?Wq`e>ue2&9>Sm>YAgfdziSNN6+3jf%Jp05DeQQ zg*gzS%GJl!*VQkCgFyi(B@>c=6r>zvEzE%sWx*jqo__A}P}Q7Z2XY3b#sL+ARf9qi R_000233jqKC0001Q0B-;|00011WpZ|F_*9YvjfQB=HfML|S-!~hCpn3-GEp^cDNm@}*38#BQ-c%L)1Gz)s1CFa>UXL$^R%{(=@8z%8VVB##VdMCm%k7qXze-UD_<9Sr ziqV=`WG7Gu?puoeOO*fI=FOY69xTdq#=l282k=2`p}=xyRum$~7-n!AUf2!ApM`i6 zwF3^urrFAw`FcN8j``9}%hG!KVqG>#to2G# zR+ph{z3+-yM*D@asV_15SmVvIm1#WI`8sd7G4Yj~kHc5irHdu<}~X^i#0sh63i z_fb^!Io<8AVnP(IN6hYO1GkFey4X9g^YV~17DsuiyE z@|z=lst~hIs2gLg^Pbp`kMtPsd**k~T{zf#Z2#QBr6`lzhzhig`8;E?LUs5X%I$yy zL}e!%3e|yaXtq8uVq$dr${h@ZcD^gtm6kTnLwK4kt-P#oA%D2?b-LC=AM04BZ>?C% z$vW2hYTn9Yot{;!`77Iwi@&m5=r}2lOOFtLWqwvXmAtNFmwm2u&7<|yv8#M#`f$r@ zyq2qvvyLnE${B$J;d`RvD-e&gGs~zxBkN2*S|6kJF_LDU()P$n<$I&?j}aGCI{FrI zmqX)z+(F=wEEV-i<7v+xG$snX3Yt_u$8hEB7pM#I)8R_wmaoD*R_URuIIRDrF8R>B&bY=b3W7GAvt^J;dY;zlj zW7{Ux%f`tx&8u~wAIxwU>h|qX!dS!&*x21i<1Kz*`#BUFW9`eNF(5->E&TlM=qQbU zOTbcx>#?y8se_Jf`snshndif#DN8=-rsZm#eX%aHa6u{a%dSkcI8*5^SF{%b5y45vP?I_E$9bq#|$g5HDF8AA4YMb zej9B!qy1;N;{eB=Hf)^F+Qv7g>G8WVU#C~bfDDB-7~gh^j^2!Txca%ucY%w#n>v|e zuW$U#1INw8a$n;s(~&h4Zh$@Sh>j@VrC(O*b0Fi-kjWo$^9eT;8w%F}`=;oK99ik5 zd5#7r$DP%X!)rxe@43Q_=R7n|=h4?yRR`d+pl|l#`Mm=N7`NY64J@h2jR6&xzqsj; z$4+ncoLMzJy|WIQ*gJ97%-UI#X7yGdG-=Z8Db)wfu9;JPpf1aJg1YRbUV5EU>o{~5 znpvFtG=K(i4sjgICV6U|XpY!(zM|$s#7on>}=mUVZ zIPZT97x)aHDiZ!tpgD*XN_Eql3WmtCU7!3mFzkTRjh#(RWgz1KMU)is@OKBDbp$ea zzO7$6YkuFt-aOBj)(}%bF>NV&6i6)oGkIcgBlBp$9e0r#rPQvE=9pw!biE;$TZ4O> z4E+`Lbu#!jW$^0(r$*_g7^9@-urVBvk_cP@B$1aE3Nyv%Ilz$g6}Wb$-S*V)lxK+1M~_#R|ZwJmMA3}zho z7-k|Uf0x=Z>{S%q}}vc zm@S7rheO+6@ zlxgl$zRUBEB9q-FWxIb2aMHWaIm}&%io48GagQT2-5G2i7_YD}{v3>gQQ#NDR*2@g zeEWnN_3Ln7tQNQ zOY`~%2of}}Wq_}+z}tWoz}u6-UCps08N46Lud*oLDT8;(;D^iLMYL2Pk*kIvUnt;RSiDkf3M#{<7Niz7!GWaPn_}PGSs@GPiYbv&5K*zo{ z_#AkSOowx2@bhHwNPJQ+B~1ia;P^>lxJ&cN zfYO@r&P7BQate_6cx`rJ4-{ahMjE^4wJxb24I+K5<6xizb>tHKF+iE;Tq<(`rvZph zDj$DbfSnF(N?Ys0P@k87B7;8xIO*Mu!zX+^Cg9AUggzMPK!y2K z=VF%t{%INfbQ%0=8T_Y!n+y0zP_cUdY$A=i3T1I-Ba+^2Jnl z>zoNP-n1T(wYIg)Xsc^(E|zBGTZ^e~qCN|Z{E@1?qps9Y*VcetYd|sQPW)}`d+lQz3hWp{_tYQA^F1#b%*6!@w>|S z&Q_GO258`%gZv5tm|wnRm2~ale}U#isIjf^$?lr!>gGd^GBrp_^O98wlgVeo-$m$u z0F6)D6~lkZ;QSjPf%Gw0u@S&`kimD7!B@!O7Xlt{xk($%MKa+R1J2b7t)<~qxr;N3UGS=eGX_r%i~>*>4kqDXnb;w2&S*heV^%H z0GPE$JcEfd_kA2+%z)#v3^*#vjl%7z&k;HYuALD>e_ruTfWd-Q80*p`U zPQFHnze$L{S&09x5YMMp@Ja2zTLG4yZg0zg|XCiWkY?$IIY+kApz@0l?F@*Fl-^#WMI38T+)6_=;Xo5zns0xu={`}zjE7xnZH&eeZp z#2(0vtHHdbZAOW=_~W1~utb&RoelHBOIhtLoo)4nGKg_NG)vJiGb}(N{|TkFsjgl< zS3&atD4-HVc~jWn>29LXi3EwhU=d_5m5_jxOk;VM2{pZ5|IOC)YKTr%aw$ zJ*n)UzzpS7<)G*m=Na}6ATgc2gFx~J*S3OkJRasKH8vG-yHY}@8`>=f6<-t8+1h~L zYb8ueQk!!^YUI*LdwpwbcWYf+N7471MprvH2}~)Q(8++3*0~n!lKJWMGEV_CUEBFg zYUHV@k*B3bo}L zGgX@9i%mvTaNi6UfP%wW&*H&8ABS$uN(FkY!PT^F=~ z3`|4uRB370XRjHNSkL>0Tw+_(L%$PgocQg|h9A}dOTYWy_2g3eCK38(pjmP0F3}oL zN!0w{65dM9Ka{fum*%DLg^CN>0;peY7qT@%jvZ^&6^Sn7C&TJeC09>ulfm1=aF^np z>7iZep+}~N9+e*Yuj!%xK1`@FX*?QGd~!AUMb5XqxoW2yK;G!seq?(`p&36V6q{OR z~*H5jaAyJcD%Idg^hh3QrA12o+r za(q~*Zzvd$!50Hw1sC!K!i6L13#}b|mHG5yNj)5ahb7Q}iuL(Ile&0|?gwr+d|tNe zs+c8VC0)=H!cd=kPL#oy%HYcY=X$`vVE^J-gNyrn%e-YAxU4@bEZ+q^J3aKA^w4v| zP+xVO2RJ9bt!-PbG>ggB2nIqY8 zCg<}l^&KtK3vKzD3H#@3t7|8lrOo{^HygC`P$uzpoP(LK1m^JwH8y}4>DPI*|6~R4MvOej{uynxuVe}ls!jpgwG&^Rq$FKhD=FM{= zVFp9)OEZz=~?PR#<+P16;e2~ju)@i5>9QW1OnA5`aTi*ei3>-(1I@WfJpd*BJ@Kd z^ah#XKN1Q5i3q(>gnn3regx=1dto+8DVO&hS z2^9Fa?|RmKv8~+>Cue@uY=fPdkN8i@ibd zjD=!sM1ki=jRsq`s|^_oieFnOJ_HJU%Dbpdhdn^>tc744(5#K}CvR*FyMf{N7KXhd zhVrXd8^e3S@SKHVUog;6Pw$|LoA8J1wOAoBh6kkPa+hPevLoVB0dIXPxPSg8jx!s* zVRtCpjzs2{8!?oP9TQ!t!CDdedm{85Kqqh>N-4uDRlidPzbldM&pf|*^WIpNq7r7P zM#W?OAozTR##bs|o2=ou;B$oHj}430{r5?DU|)Ek(t=Ncf@$t{rx_jxLzRVLZjgce zF7&*x2|oC7fU^Q8;mJEh*5Jd>kHpvdU#0KTeu2pLg+a9T{U-Rn*5doVAOnqep%($2 zr1iV-{Xywk|BcXpvPJ)aAOrPxp$CDcgut-vf-e>cUm_EJf((A548BwbUnYZ}1bC8m z=c>4qfoHpLk6FG}^Xahiy4h|(vz=;bwx0=8Py-kI)I|Eb(5H#er;E^M$P7O-f;V-> z?oWriRPg!jEWlA4`1!b{p|c*ZnJTn-|3As)!Lwy*oFjvuD}$dWgD(f1b5;DHR#&Qb z--P3 z+okzeMCh*qjZZF>)4mpou5sSt;;XRLk?4tOYWvDabh>tWl?Z*c2z`wReQhGN>tgG> zBJ?dH^sOTFZ9pfP@VYF&U5H;R(*6#h6I^Dwl)qCX{4SaByTfoj*>_##KAcE@7y6N~ z0vu*s@W*8ECuHy^W$>qD@Lxvo1gq1oE5+Y|!apI@3;;xxcowX*8m`vxwqdBT4h?d;r9r+uQX_#!?*&Dph2q_yz$Y-%cAM&gE@AAMW!W1;X1wRCt%y%~@ANo*a2F%y`yIgQxa*7*Jg-2Pc@S9-@8sQoo z|Bwvs8lFD@3j;o&bQgRN8GIbzr1#gKOZZ+g;d{&A`^exQ0UURL=MFD6bR5#1Y9V1? znFjj-9vTCEb-%w5KOXq>m0uM^qkuY7xO&b3RtDSn?V40ngMm^4R(7*?OR~Q~LU_+RK8qf!N!|qV1!4DqchO3b*X@*)6 zdV&aDAEDFz8G5rwc1eVu9iiR#vzj$l>GR$QU4FBkSt~yDe4w!$;a{%T)y>!planoE zXn3XOO@Lzz$VG2W=*GRY&i6I>Y$$<;4@q|MiNBhI4w_)a+V!054H{^a7`fx(`9-TcAc{+@he>x{bmhufD94E8SQ z>g}I9zwg+On4U2AwO;g&s{JUl5zO@VF!YL$jAn??hltQc5&BRO`Y;i?NrY}rghu6z z;Ye4%bk=;lvnk)j>f)^TOfdqKI+=l1xD3GVad z9~>+6{yU9*{^hPt=b2jX^YLo#6URjY?&C$Kn|Cty`KAD!PI;JUs4^_~3^vN&gqY2j z<@Uz5AGQ@Q-~kV$V>fpizc{$50geX@l&TYm-1;RbQ7Q!;Jirky!TOWxpckft47`x=j4eEV@H)=l_toeyJjHlH=qFVrOwugoW2z;a zq~QeB)x!{PHH4+aN`&X9E0Vd;t5|E0Lz(a8P^x=NgezOET6;Od*OlRU;fI3Os#_Jj zdW5arHYF0ygS-tl+@t6Ue>dGW*3t~W9=S)b<7W?Vdgs9p#6Ji{(1U32g zLc*lsQ$bAZR!L9}8VgS=m7`iLtIC)y>S-#k`CCQPEJ$OvWI_50alD#rd4*hYl*3gtc$Hx7!(WeLU${{gZj;So6RPQpx?qe_ zE$T8bLaZ8Ip@i5d zr8Ip8SKs>5{3hJzqH0a$u#y;J<}+7Nf-gJtOHnt&#>AQlAEIJjJ$iyARt8Iq4VF+< z>D5C`(7YwW9Gf!GBP>Nyf_1}iC2xY_fjYe--pJJ+ulXM*&RasF7>OB1IkNA_qdpz= zDY};KVyd5+gY>JZeW>e~?P8SLel&eGwGY(^wu|<${diqnu6TX=YV!IE96!C*?innh zCh}emH81m)7%A-|T({woE_??7|1i<-^^xL_Q9ZWT*;cqEkJjz>TDMu$+-UoFE!Tb) zEhu~@%tDG<Ic|Mv*gushTZmUXh-0@m^dK?rWD}wk^Cn!R4bxJ{Sw@=hXE3i6w}Z6Ua0yk? zD@Bc`-V!l?gh^wN6bZ50EMhLDDiST`ncEw_K z8`dKRi6vM$Sc>5u_FHQSCNgB<5Bo3Prl#S?DzeZ+{njY7HoW|!dV^Pr^1io3_)%H@ zU5vlx{uwM0_GuHx9IvKf4tELN3ZK{aTI+;encx+BGwae?LUZu%cPX$@rA`w0ngljH*!U=OI ztGBw>vv{^T3r)Apx8kkX^T3)m zrA4}~S_-|eEDO`wv%3SkGvmxGcGHKEP=&>$0xf}{CN;j)gh-6WL=BgOq!fun5YdDe z6Kj0KCogYA5+Cq^cu5sW0RR8r`Db@K-QDEm%%1a||91ZWoU=pB67@oei=Q5eLMK*2 zTM8`|?{f{)(G1=@Dv2d*r^UAO~nm_)*7n6;% z3u2ag^Kofudu7}+KDs&F5qrXiTfrhUssh{%aJ>(|3t$zv6X3Z%JWw6p3hA2N6~a?HBtuFG(38nxh18XEfq^mxqD=8kvIqwdH40!vk<~_&=&fjttIu0 z)SboR4;b4vb+wtJ%;{_!Sxc3mHe(t(kWJzsP8pU%+T3{Ga*A>Psqs-($OY%*ObI{>$${ncLkNN4k-?c?DBXM(`%~GZl4j)t)e^wihj6k12nSW@V@-fXo)T1lJD4R z@ilNq?tV7Ts^-FfG)zrt<{FZEeQ4@i7^Gd{qK2*2oSd81`YgrDxu&97Pl=ZRN}s;= zBg4(`fua&x8logksmGc}C&^m$jF?Rbw1Z~6J@oT9_tq;`FPETvF zmi+XHMAVGwLP|MVdxo0YK#JaI?>-Hp$ZbA@)wH4R!7XYHsNGdj?evbZ;iwRkg4<0lU!@rH{J)K-^)2`bsa2su= z3i|F$^euLPQy1J7OSsq_X8m0>*Pr~R4_!|Kjb0&Ba6zi#?yS?;? zI`zu0aaPGGP+UxUw~=1l3I^dNC0?*|nTQyLuPg7o`2dRzFDbsL=x&BbSQc+ndwan0 zncoA7ns9lMOIHuR70TZO(Lhk~(!(ftkHgRo+M9bjuMNXQ+398~76cO>qW=Q`0RR6b Cl(uL9 literal 0 HcmV?d00001 diff --git a/Quartus/A2/db/assignment2.sld_design_entry.sci b/Quartus/A2/db/assignment2.sld_design_entry.sci new file mode 100644 index 0000000000000000000000000000000000000000..7a5b911bc97025e01fac4c7ee13ae5fa692fcce6 GIT binary patch literal 229 zcmWe(U|?9w%?KnJ81jM80!W9Y78Pga=P4MO>KPW7r05waIF)ARq$n5~8d)kB8t5At z>KhptnJNT3EBIuVq$;?kWR?KcyMYa1U}%QY#ZVeVJ%zF>7?TneSU)g`{�q_zM#J z{~supmXH#0@W6qDTYEx#1wD)z4b27Et*eji-oaMA>$jm{0mDxNhM>dDM~L4}%0PI^v A!~g&Q literal 0 HcmV?d00001 diff --git a/Quartus/A2/db/assignment2.smart_action.txt b/Quartus/A2/db/assignment2.smart_action.txt new file mode 100644 index 0000000..11b531f --- /dev/null +++ b/Quartus/A2/db/assignment2.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/Quartus/A2/db/assignment2.tis_db_list.ddb b/Quartus/A2/db/assignment2.tis_db_list.ddb new file mode 100644 index 0000000000000000000000000000000000000000..781db1ed68903d6716948121a6a5be6d886c52a7 GIT binary patch literal 242 zcmWe(U|?9w%?KnJ81jM80!W9Y78Pga=P4MO>KPW7r05waIF)ARq$n5~8d)kB8t5At z>KhptnJNT3EBIuVq$;?kWR?KcbASzDV5o-Dbx;~aeS)$p7?Tnk!0iA3f$XG&6oZ6> zgbRXyf)8^nnb{B_*Wql_{5W>bqgvU&GIwK}A2G)?H`z8j$NY7AWc&BdpP3RC4Os~c zOU_GlbbAM_S;Hk{+?^97 ; -- ; -- ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 400 MB ; 00:00:25 ; +; Total ; 00:00:10 ; -- ; -- ; 00:00:25 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+---------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+---------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; ++----------------------+---------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 + + + diff --git a/Quartus/A2/output_files/assignment2.map.rpt b/Quartus/A2/output_files/assignment2.map.rpt new file mode 100644 index 0000000..180c01b --- /dev/null +++ b/Quartus/A2/output_files/assignment2.map.rpt @@ -0,0 +1,183 @@ +Analysis & Synthesis report for assignment2 +Tue Oct 13 12:21:52 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Failed - Tue Oct 13 12:21:52 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A until Partition Merge ; +; Total registers ; N/A until Partition Merge ; +; Total pins ; N/A until Partition Merge ; +; Total virtual pins ; N/A until Partition Merge ; +; Total block memory bits ; N/A until Partition Merge ; +; Total PLLs ; N/A until Partition Merge ; +; Total DLLs ; N/A until Partition Merge ; ++-----------------------------+-------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5CGXFC5C6F27C7 ; ; +; Top-level entity name ; assignment2 ; assignment2 ; +; Family name ; Cyclone V ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 3 ; 3 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Automatic Parallel Synthesis ; On ; On ; +; Partial Reconfiguration Bitstream ID ; Off ; Off ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Oct 13 12:21:42 2026 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Error (10170): Verilog HDL syntax error at assignment2.sv(26) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Error (10149): Verilog HDL Declaration error at assignment2.sv(26): identifier "pc_we" is already declared in the present scope File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Error (10149): Verilog HDL Declaration error at assignment2.sv(26): identifier "pc_addr" is already declared in the present scope File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Error (10170): Verilog HDL syntax error at assignment2.sv(26) near text: ")"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Error (10170): Verilog HDL syntax error at assignment2.sv(27) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 27 +Error (10170): Verilog HDL syntax error at assignment2.sv(28) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 +Error (10170): Verilog HDL syntax error at assignment2.sv(29) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 29 +Error (10112): Ignored design unit "assignment2" at assignment2.sv(20) due to previous errors File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 20 +Info (12021): Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv +Error: Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 1 warning + Error: Peak virtual memory: 400 megabytes + Error: Processing ended: Tue Oct 13 12:21:52 2026 + Error: Elapsed time: 00:00:10 + Error: Total CPU time (on all processors): 00:00:25 + + diff --git a/Quartus/A2/output_files/assignment2.map.summary b/Quartus/A2/output_files/assignment2.map.summary new file mode 100644 index 0000000..473bad4 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.map.summary @@ -0,0 +1,12 @@ +Analysis & Synthesis Status : Failed - Tue Oct 13 12:21:52 2026 +Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Revision Name : assignment2 +Top-level Entity Name : assignment2 +Family : Cyclone V +Logic utilization (in ALMs) : N/A until Partition Merge +Total registers : N/A until Partition Merge +Total pins : N/A until Partition Merge +Total virtual pins : N/A until Partition Merge +Total block memory bits : N/A until Partition Merge +Total PLLs : N/A until Partition Merge +Total DLLs : N/A until Partition Merge diff --git a/modules/assignment2.sv b/modules/assignment2.sv index ed1d9f7..f934ee3 100644 --- a/modules/assignment2.sv +++ b/modules/assignment2.sv @@ -1,8 +1,20 @@ -`include "rom.sv" -`include "ram.sv" -`include "instruction_counter.sv" -`include "instruction_classifier.sv" -`include "alu.sv" +`ifndef ASS_2_SV +`define ASS_2_SV + +`ifdef SYNTHESIS + `include "../../rom.sv" + `include "../../ram.sv" + `include "../../instruction_counter.sv" + `include "../../instruction_classifier.sv" + `include "../../alu.sv" +`else + `include "rom.sv" + `include "ram.sv" + `include "instruction_counter.sv" + `include "instruction_classifier.sv" + `include "alu.sv" +`endif + module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk); @@ -16,4 +28,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk); RAM ram #(ramsz, 2**width)(); alu alu #(width)(); -endmodule \ No newline at end of file +endmodule + +`endif \ No newline at end of file diff --git a/modules/assignment2.sv.bak b/modules/assignment2.sv.bak new file mode 100644 index 0000000..ed1d9f7 --- /dev/null +++ b/modules/assignment2.sv.bak @@ -0,0 +1,19 @@ +`include "rom.sv" +`include "ram.sv" +`include "instruction_counter.sv" +`include "instruction_classifier.sv" +`include "alu.sv" + + +module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk); + + logic [romsz-1:0] pc_addr; + logic [0:0] pc_we; + logic [2**width-1:0] instruction; + + instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr); + ROM rom #(romsz, 2**width)(); + RAM ram #(ramsz, 2**width)(); + alu alu #(width)(); + +endmodule \ No newline at end of file diff --git a/modules/instruction_counter.sv b/modules/instruction_counter.sv index 2b58410..780b99a 100644 --- a/modules/instruction_counter.sv +++ b/modules/instruction_counter.sv @@ -8,14 +8,14 @@ module instruction_counter #(parameter width=5)( ); logic [2**width-1:0] pc; - always_ff (@posedge clk) begin + always_ff @(posedge clk) begin if (we) begin - pc <= W - else + pc <= W; + end else begin pc <= pc + 4; end end assign addr = pc; endmodule -`endif \ No newline at end of file +`endif diff --git a/modules/ram.sv b/modules/ram.sv index d1199b8..135161a 100644 --- a/modules/ram.sv +++ b/modules/ram.sv @@ -1,4 +1,7 @@ -module rom #(addrwidth=9, datawidth=5)( +`ifndef RAM_H +`define RAM_H + +module ram #(addrwidth=9, datawidth=5)( input logic [0:0] clk, input logic [2**addrwidth-1:0] addr, input logic [0:0] we, @@ -15,11 +18,13 @@ module rom #(addrwidth=9, datawidth=5)( end end - always_ff(@posedge clk) begin + always_ff @(posedge clk) begin if (we) begin mem[addr] <= data_in; end end assign data_out = mem[addr]; -endmodule; \ No newline at end of file +endmodule + +`endif diff --git a/modules/rom.sv b/modules/rom.sv index f22d843..80e6a4b 100644 --- a/modules/rom.sv +++ b/modules/rom.sv @@ -1,3 +1,5 @@ +`ifndef ROM_H +`define ROM_H module rom #(parameter m=7,p=4) ( input logic [m-1:0] Ad, @@ -17,3 +19,5 @@ module rom #(parameter m=7,p=4) ( `endif end endmodule // end rom module + +`endif