Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

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riley committed 2026-09-03 16:05:52 +10:00
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commit 6668969b03
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`include "asu.v"
module asu_tb #(width=8)();
logic [0:0] op;
logic [width-1:0] A;
logic [width-1:0] B;
logic [width-1:0] C;
logic [0:0] Cout;
logic [0:0] Cin;
logic [width-1:0] C_exp;
logic [0:0] Cout_exp;
logic [0:0] Cin_exp; // TODO
logic [0:0] Signed_overflow;
asu #(width) dut(op, A, B, C, Cout, Cin);
integer error_count;
initial begin
error_count = 0;
$display("Beginning ASU tests");
// Test basic addition of 0+1 = 1
op = 1'b0;
A = {width{1'b0}};
B = { {(width-1){1'b0}}, 1'b1};
C_exp = { {(width-1){1'b0}}, 1'b1};
Cout_exp = 1'b0;
Cin_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
// Test underflow from 0-1 = UINTMAX
op = 1'b1;
C_exp = {(width){1'b1}};
Cout_exp = 1'b0;
Cin_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
// Test carry addition of 1+1 = 2
op = 1'b0;
A = { {(width-1){1'b0}}, 1'b1};
B = { {(width-1){1'b0}}, 1'b1};
C_exp = { {(width-2){1'b0}}, 2'b10};
Cout_exp = 1'b0;
Cin_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
// Test overflow from UINTMAX+1 = 0
A = {(width){1'b1}}; // UINTMAX
B = { {(width-1){1'b0}}, 1'b1}; // 1
C_exp = {(width){1'b0}};
Cout_exp = 1'b1;
Cin_exp = 1'b1;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
// Tests INTMAX+1
op = 1'b0;
A = {1'b0, {(width-1){1'b1}}}; // INTMAX
B = {{(width-1){1'b0}}, 1'b1}; // 1
C_exp = {1'b1, {(width-1){1'b0}}}; // -INTMAX
Cin_exp = 1'b1;
Cout_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
op = 1'b0;
A = {1'b1, {(width-1){1'b0}}}; // -INTMAX
B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
C_exp = {width{1'b0}}; // 0
Cin_exp = 1'b0;
Cout_exp = 1'b1;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
op = 1'b1;
A = {1'b0, {(width-1){1'b1}}}; // INTMAX
B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
C_exp = {width{1'b1}}; // -1
Cin_exp = 1'b1;
Cout_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
op = 1'b1;
A = {1'b1, {(width-1){1'b0}}}; // -INTMAX
B = {{(width-1){1'b0}}, 1'b1}; // 1
C_exp = {1'b0, {(width-1){1'b1}}}; // INTMAX
Cin_exp = 1'b0;
Cout_exp = 1'b1;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
if (error_count == 0) $display("\x1b[38;5;10mAll ASU tests passing\x1b[m");
else $display("\x1b[38;5;9m%0d ASU test(s) failing\x1b[m", error_count);
end
endmodule