Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

tests/alu_tb.sv

@@ -0,0 +1,6 @@
+// TODO: Both the ALU and this test bench is incomplete
+`#include "alu.v"
+
+module alu_tb #(width=8)();
+
+endmodule