Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

modules/instruction_classifier.sv

@@ -0,0 +1,25 @@
+module instruction_classifier(input logic op[5:0],
+    output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
+    output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
+    output logic[0:0] M);
+
+    logic [6:0] OUT_1;
+    casez (op)
+        6'b1?????: OUT_1 = 7'b1000000;
+        6'b01????: OUT_1 = 7'b0100000;
+        6'b001???: OUT_1 = 7'b0010000;
+        6'b0001??: OUT_1 = 7'b0001000;
+        6'b00001?: OUT_1 = 7'b0000100;
+        6'b000001: OUT_1 = 7'b0000010;
+        6'b000000: OUT_1 = 7'b0000001;
+    endcase
+
+    assign R  = OUT_1[6];
+    assign B1 = OUT_1[5];
+    assign J  = OUT_1[4];
+    assign B2 = OUT_1[3];
+    assign I  = OUT_1[2];
+    assign F  = OUT_1[1];
+    assign M  = OUT_1[0];
+
+endmodule