Made sign extension explicit to remove bit indexing (which iverilog doesn't like) and a tad more readable.

modules/sign_extender.sv

@@ -6,9 +6,11 @@ module sign_extender #(in_width=4, out_width=5)(
     input logic [2**in_width-1:0] val,
     output logic [2**out_width-1:0] ext_val
 );
+    logic [0:0] msb;
+    assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
     always_comb begin
         if (op) begin
-            ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
+            ext_val = { {(2**(out_width-in_width)){msb}}, val};
         end else begin
             ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
         end