From 65be2c2d6169bc507ad9422a8bc3d4eb1535cb3c Mon Sep 17 00:00:00 2001 From: Riley King-Saunders Date: Fri, 16 Oct 2026 11:35:24 +1100 Subject: [PATCH] Made sign extension explicit to remove bit indexing (which iverilog doesn't like) and a tad more readable. --- modules/sign_extender.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/modules/sign_extender.sv b/modules/sign_extender.sv index 77a9ae1..a0e2ef9 100644 --- a/modules/sign_extender.sv +++ b/modules/sign_extender.sv @@ -6,9 +6,11 @@ module sign_extender #(in_width=4, out_width=5)( input logic [2**in_width-1:0] val, output logic [2**out_width-1:0] ext_val ); + logic [0:0] msb; + assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1); always_comb begin if (op) begin - ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val}; + ext_val = { {(2**(out_width-in_width)){msb}}, val}; end else begin ext_val = ({{(2**(out_width-in_width)){1'b0}}, val}); end