Updated RAM code to make sure Bus width is 32 bits

modules/assignment2.sv

@@ -12,7 +12,7 @@
 `include "seven_seg_4digit.sv"
 
 
-module assignment2 #(width=5, ramsz=9, romsz=10) (
+module assignment2 #(width=5, romsz=10) (
 	input logic [0:0] clk
 `ifdef QUARTUS_SYNTH
     ,
@@ -51,13 +51,17 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] rd;
 	logic [0:0] rd_we;
 	logic [31:0] regs_out [32];
+
+    // ALU intermediates
+	logic [2**width-1:0] rd_alu;
+	logic [2**width-1:0] rt_alu;
 	
 	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
 	
 	rom #(romsz, 2**width) ROM (pc_addr, instruction);
 
 	logic [2**width-1:0] rd_mem;
-	ram #(ramsz, 2**width) RAM (clk, rd_alu, M2W, rt, rd_mem);
+	ram #(width) RAM (clk, rd_alu, M2W, rt, rd_mem);
 	
 	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
 		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
@@ -78,8 +82,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
     //  - ALU srcB
     //  - PCBranch (rel jump of 4-byte words)
 
-	logic [2**width-1:0] rd_alu;
-	logic [2**width-1:0] rt_alu;
+
 	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
     assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);