diff --git a/ModelSim/Assignment_1_Q2.cr.mti b/ModelSim/Assignment_1_Q2.cr.mti index b544ff0..1b10750 100644 --- a/ModelSim/Assignment_1_Q2.cr.mti +++ b/ModelSim/Assignment_1_Q2.cr.mti @@ -1,11 +1,4 @@ -/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv -Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 --- Compiling module lu - -Top level modules: - lu - -} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv +/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -- Compiling module lu -- Compiling module lu_tb diff --git a/ModelSim/Assignment_2.cr.mti b/ModelSim/Assignment_2.cr.mti new file mode 100644 index 0000000..ca7cdef --- /dev/null +++ b/ModelSim/Assignment_2.cr.mti @@ -0,0 +1,206 @@ +/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module shifter + +Top level modules: + shifter + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module rom + +Top level modules: + rom + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module instruction_classifier + +Top level modules: + instruction_classifier + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module seven_seg + +Top level modules: + seven_seg + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module ram + +Top level modules: + ram + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module instruction_classifier +-- Compiling module control_unit + +Top level modules: + control_unit + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module rom +-- Compiling module ram +-- Compiling module register_file +-- Compiling module instruction_counter +-- Compiling module instruction_classifier +-- Compiling module control_unit +-- Compiling module asu +-- Compiling module lu +-- Compiling module alu +** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(1) +** while parsing file included at assignment2.sv(9) +** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block. +-- Compiling module shifter +-- Compiling module sign_extender +-- Compiling module seven_seg +-- Compiling module seven_seg_4digit +-- Compiling module assignment2 +-- Compiling module mips_tb + +Top level modules: + shifter + mips_tb + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module asu + +Top level modules: + asu + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module lu + +Top level modules: + lu + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module shifter +-- Compiling module shifter_tb + +Top level modules: + shifter_tb + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module rom +-- Compiling module ram +-- Compiling module register_file +-- Compiling module instruction_counter +-- Compiling module instruction_classifier +-- Compiling module control_unit +-- Compiling module asu +-- Compiling module lu +-- Compiling module alu +** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv(9) +** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block. +-- Compiling module shifter +-- Compiling module sign_extender +-- Compiling module seven_seg +-- Compiling module seven_seg_4digit +-- Compiling module assignment2 + +Top level modules: + shifter + assignment2 + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module seven_seg +-- Compiling module seven_seg_tb + +Top level modules: + seven_seg_tb + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module asu +-- Compiling module asu_tb + +Top level modules: + asu_tb + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module lu +-- Compiling module lu_tb + +Top level modules: + lu_tb + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module sign_extender + +Top level modules: + sign_extender + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module asu +-- Compiling module lu +-- Compiling module alu +** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv(1) +** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block. +-- Compiling module alu_tb + +Top level modules: + alu_tb + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module instruction_counter + +Top level modules: + instruction_counter + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module asu +-- Compiling module lu +-- Compiling module alu +** Warning: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block. + +Top level modules: + alu + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module rom +-- Compiling module ByteIM + +Top level modules: + rom + ByteIM + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module seven_seg +-- Compiling module seven_seg_4digit + +Top level modules: + seven_seg_4digit + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module instruction_classifier +-- Compiling module instruction_classifier_tb + +Top level modules: + instruction_classifier_tb + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module register_file + +Top level modules: + register_file + +} {} {}} diff --git a/ModelSim/Assignment_2.mpf b/ModelSim/Assignment_2.mpf new file mode 100644 index 0000000..62dffb1 --- /dev/null +++ b/ModelSim/Assignment_2.mpf @@ -0,0 +1,506 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +maxii = $MODEL_TECH/../altera/vhdl/maxii +maxv = $MODEL_TECH/../altera/vhdl/maxv +fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm +sgate = $MODEL_TECH/../altera/vhdl/sgate +arriaii = $MODEL_TECH/../altera/vhdl/arriaii +arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi +arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip +arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz +arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi +arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip +stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv +stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi +stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip +cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv +cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi +cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip +cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive +stratixv = $MODEL_TECH/../altera/vhdl/stratixv +stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi +stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip +arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz +arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi +arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip +arriav = $MODEL_TECH/../altera/vhdl/arriav +cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev +twentynm = $MODEL_TECH/../altera/vhdl/twentynm +twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi +twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip +cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp +; +; Verilog Section +; +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +maxv_ver = $MODEL_TECH/../altera/verilog/maxv +fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii +arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi +arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip +arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz +arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi +arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip +stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv +stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi +stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip +stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv +stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi +stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip +arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz +arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi +arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip +arriav_ver = $MODEL_TECH/../altera/verilog/arriav +arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi +arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip +cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev +cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi +cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip +cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv +cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi +cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip +cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive +twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm +twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi +twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip +cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 1 ns + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 22 +Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792107144 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_2 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv +Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_3 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv +Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_4 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv +Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792039197 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_5 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv +Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792040117 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_6 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv +Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792104861 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_7 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv +Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228118 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_8 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv +Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_9 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv +Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_10 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv +Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792106709 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_11 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv +Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788418794 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_12 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv +Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_13 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv +Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_14 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv +Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792038654 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_15 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv +Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv +Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1791854498 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv +Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792036226 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_18 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv +Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792106811 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv +Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1791866874 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_20 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv +Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv +Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792035553 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2020 +Project_Minor_Version = 1 diff --git a/ModelSim/ByteIM.sv b/ModelSim/ByteIM.sv index 6e913a7..ef70d34 100644 --- a/ModelSim/ByteIM.sv +++ b/ModelSim/ByteIM.sv @@ -10,5 +10,5 @@ module ByteIM #(parameter m=5,n=2) ( // 2**(m-n) memory words // 2**(n+3) bit wide words // Reads the whole word that contains the addressed byte - ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout) + ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout); endmodule diff --git a/ModelSim/assignment2.sv b/ModelSim/assignment2.sv index 36426c5..716d8f7 100644 --- a/ModelSim/assignment2.sv +++ b/ModelSim/assignment2.sv @@ -13,9 +13,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( - input logic [0:0] clk -`ifdef QUARTUS_SYNTH - , + input logic [0:0] clk, input logic [4:0] HID_Register, input logic [0:0] HID_PC, input logic [0:0] HID_Hi_Low, @@ -24,7 +22,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( output logic[7:0] out_seg_1, output logic[7:0] out_seg_2, output logic[7:0] out_seg_3 -`endif ); // Intermediate for displaying high / low of PC or Register logic[15:0] PC_Reg_Display; @@ -51,6 +48,10 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( logic [2**width-1:0] rd; logic [0:0] rd_we; logic [31:0] regs_out [32]; + + // ALU intermeduates + logic [2**width-1:0] rd_alu; + logic [2**width-1:0] rt_alu; instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr); @@ -78,8 +79,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( // - ALU srcB // - PCBranch (rel jump of 4-byte words) - logic [2**width-1:0] rd_alu; - logic [2**width-1:0] rt_alu; alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]); assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt); diff --git a/ModelSim/rom.sv b/ModelSim/rom.sv index e18e3c7..f41020f 100644 --- a/ModelSim/rom.sv +++ b/ModelSim/rom.sv @@ -15,7 +15,7 @@ module rom #(parameter m=7,p=4) ( `ifdef QUARTUS_SYNTH $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary `else - $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary + $readmemh("../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary `endif end endmodule // end rom module diff --git a/ModelSim/rom.sv.bak b/ModelSim/rom.sv.bak new file mode 100644 index 0000000..e18e3c7 --- /dev/null +++ b/ModelSim/rom.sv.bak @@ -0,0 +1,24 @@ +`ifndef ROM_H +`define ROM_H + +module rom #(parameter m=7,p=4) ( + input logic [m-1:0] Ad, + output logic [p-1:0] Dout + ); + + logic [p-1:0] mem[2**m-1:0]; + assign Dout = mem[Ad]; + + //Load the program in memory + // The machine code stored in text file program.dat written in Hex format + initial begin + `ifdef QUARTUS_SYNTH + $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary + `else + $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary + `endif + end +endmodule // end rom module + +`endif + diff --git a/ModelSim/transcript b/ModelSim/transcript index 16838a3..bbc6bf7 100644 --- a/ModelSim/transcript +++ b/ModelSim/transcript @@ -1,21 +1,1109 @@ # Loading project Assignment_1_Q2 -vsim work.lu_tb -# vsim work.lu_tb -# Start time: 16:47:26 on Sep 15,2026 +# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini +# Loading project Assignment_2 +# Compile of alu.sv was successful with warnings. +# Compile of alu_tb.sv was successful with warnings. +# Compile of assignment2.sv failed with 3 errors. +# Compile of asu.sv was successful. +# Compile of asu_tb.sv was successful. +# Compile of ByteIM.sv failed with 1 errors. +# Compile of control_unit.sv was successful. +# Compile of instruction_classifier.sv was successful. +# Compile of instruction_classifier_tb.sv was successful. +# Compile of instruction_counter.sv was successful. +# Compile of lu.sv was successful. +# Compile of lu_tb.sv was successful. +# Compile of mips.sv failed with 3 errors. +# Compile of ram.sv was successful. +# Compile of register_file.sv was successful. +# Compile of rom.sv was successful. +# Compile of seven_seg.sv was successful. +# Compile of seven_seg_4digit.sv was successful. +# Compile of seven_seg_tb.sv was successful. +# Compile of shifter.sv was successful. +# Compile of shifter_tb.sv was successful. +# Compile of sign_extender.sv was successful. +# Compile of tests.sv failed with 6 errors. +# 23 compiles, 4 failed with 13 errors. +# Compile of assignment2.sv failed with 3 errors. +# Compile of assignment2.sv failed with 1 errors. +# Compile of assignment2.sv failed with 1 errors. +# Compile of assignment2.sv was successful with warnings. +# Compile of mips.sv was successful with warnings. +# Compile of ByteIM.sv failed with 1 errors. +# Compile of ByteIM.sv was successful. +# Compile of alu.sv was successful with warnings. +# Compile of alu_tb.sv was successful with warnings. +# Compile of assignment2.sv was successful with warnings. +# Compile of asu.sv was successful. +# Compile of asu_tb.sv was successful. +# Compile of ByteIM.sv was successful. +# Compile of control_unit.sv was successful. +# Compile of instruction_classifier.sv was successful. +# Compile of instruction_classifier_tb.sv was successful. +# Compile of instruction_counter.sv was successful. +# Compile of lu.sv was successful. +# Compile of lu_tb.sv was successful. +# Compile of mips.sv was successful with warnings. +# Compile of ram.sv was successful. +# Compile of register_file.sv was successful. +# Compile of rom.sv was successful. +# Compile of seven_seg.sv was successful. +# Compile of seven_seg_4digit.sv was successful. +# Compile of seven_seg_tb.sv was successful. +# Compile of shifter.sv was successful. +# Compile of shifter_tb.sv was successful. +# Compile of sign_extender.sv was successful. +# 22 compiles, 0 failed with no errors. +vsim work.mips_tb +# vsim work.mips_tb +# Start time: 10:28:41 on Oct 16,2026 # Loading sv_std.std -# Loading work.lu_tb +# Loading work.mips_tb +# Loading work.assignment2 +# Loading work.instruction_counter +# Loading work.rom +# Loading work.ram +# Loading work.control_unit +# Loading work.instruction_classifier +# Loading work.register_file +# Loading work.sign_extender +# Loading work.alu +# Loading work.asu # Loading work.lu -add wave -position end sim:/lu_tb/op -add wave -position end sim:/lu_tb/A -add wave -position end sim:/lu_tb/B -add wave -position end sim:/lu_tb/C -add wave -position end sim:/lu_tb/C_exp -run -# Beginning LU tests -run +# Loading work.seven_seg_4digit +# Loading work.seven_seg +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 +# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 +add wave -position end sim:/mips_tb/clk +add wave -position end sim:/mips_tb/num_errors +add wave -position end sim:/mips_tb/CPU/instruction run +# ** Warning: (vsim-7) Failed to open readmem file "./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt" in read mode. +# No such file or directory. (errno = ENOENT) : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18) +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ROM +# Beginning MIPS tests +# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[8] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[9] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[10] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[11] == 32'd14 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[12] == -32'sd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[14] == 32'd3 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[16] == 32'd2 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[17] == 32'd15 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[18] == 32'd13 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == -32'sd16 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[20] == 32'd1 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# All MIPS tests passing +quit -sim +# End time: 10:32:02 on Oct 16,2026, Elapsed time: 0:03:21 +# Errors: 0, Warnings: 27 +# Compile of alu.sv was successful with warnings. +# Compile of alu_tb.sv was successful with warnings. +# Compile of assignment2.sv was successful with warnings. +# Compile of asu.sv was successful. +# Compile of asu_tb.sv was successful. +# Compile of ByteIM.sv was successful. +# Compile of control_unit.sv was successful. +# Compile of instruction_classifier.sv was successful. +# Compile of instruction_classifier_tb.sv was successful. +# Compile of instruction_counter.sv was successful. +# Compile of lu.sv was successful. +# Compile of lu_tb.sv was successful. +# Compile of mips.sv was successful with warnings. +# Compile of ram.sv was successful. +# Compile of register_file.sv was successful. +# Compile of rom.sv was successful. +# Compile of seven_seg.sv was successful. +# Compile of seven_seg_4digit.sv was successful. +# Compile of seven_seg_tb.sv was successful. +# Compile of shifter.sv was successful. +# Compile of shifter_tb.sv was successful. +# Compile of sign_extender.sv was successful. +# 22 compiles, 0 failed with no errors. +vsim work.mips_tb +# vsim work.mips_tb +# Start time: 10:33:32 on Oct 16,2026 +# Loading sv_std.std +# Loading work.mips_tb +# Loading work.assignment2 +# Loading work.instruction_counter +# Loading work.rom +# Loading work.ram +# Loading work.control_unit +# Loading work.instruction_classifier +# Loading work.register_file +# Loading work.sign_extender +# Loading work.alu +# Loading work.asu +# Loading work.lu +# Loading work.seven_seg_4digit +# Loading work.seven_seg +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 +# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 run +# Beginning MIPS tests +# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[8] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[9] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[10] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[11] == 32'd14 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[12] == -32'sd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[14] == 32'd3 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[16] == 32'd2 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[17] == 32'd15 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[18] == 32'd13 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == -32'sd16 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[20] == 32'd1 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# All MIPS tests passing +add wave -position end sim:/mips_tb/clk run -all -# All LU tests passing -# End time: 16:52:34 on Sep 15,2026, Elapsed time: 0:05:08 +run +quit -sim +# End time: 10:42:49 on Oct 16,2026, Elapsed time: 0:09:17 +# Errors: 0, Warnings: 14 +vsim work.mips_tb +# vsim work.mips_tb +# Start time: 10:42:57 on Oct 16,2026 +# Loading sv_std.std +# Loading work.mips_tb +# Loading work.assignment2 +# Loading work.instruction_counter +# Loading work.rom +# Loading work.ram +# Loading work.control_unit +# Loading work.instruction_classifier +# Loading work.register_file +# Loading work.sign_extender +# Loading work.alu +# Loading work.asu +# Loading work.lu +# Loading work.seven_seg_4digit +# Loading work.seven_seg +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 +# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 +add wave -position end sim:/mips_tb/clk +add wave -position end sim:/mips_tb/CPU/instruction +run +# Beginning MIPS tests +# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[8] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[9] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[10] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[11] == 32'd14 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[12] == -32'sd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[14] == 32'd3 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[16] == 32'd2 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[17] == 32'd15 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[18] == 32'd13 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == -32'sd16 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[20] == 32'd1 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# All MIPS tests passing +quit -sim +# End time: 10:44:19 on Oct 16,2026, Elapsed time: 0:01:22 +# Errors: 0, Warnings: 13 +vsim work.mips_tb +# vsim work.mips_tb +# Start time: 10:47:26 on Oct 16,2026 +# Loading sv_std.std +# Loading work.mips_tb +# Loading work.assignment2 +# Loading work.instruction_counter +# Loading work.rom +# Loading work.ram +# Loading work.control_unit +# Loading work.instruction_classifier +# Loading work.register_file +# Loading work.sign_extender +# Loading work.alu +# Loading work.asu +# Loading work.lu +# Loading work.seven_seg_4digit +# Loading work.seven_seg +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 +# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 +add wave -position end sim:/mips_tb/clk +force -freeze sim:/mips_tb/clk 1 0, 0 {10 ps} -r 20 +run +# Beginning MIPS tests +# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[8] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[9] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[10] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[11] == 32'd14 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[12] == -32'sd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[14] == 32'd3 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[16] == 32'd2 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[17] == 32'd15 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[18] == 32'd13 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == -32'sd16 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[20] == 32'd1 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# All MIPS tests passing +add wave -position end sim:/mips_tb/num_errors +run +run +quit -sim +# End time: 10:49:38 on Oct 16,2026, Elapsed time: 0:02:12 +# Errors: 0, Warnings: 13 +vsim work.mips_tb +# vsim work.mips_tb +# Start time: 10:49:39 on Oct 16,2026 +# Loading sv_std.std +# Loading work.mips_tb +# Loading work.assignment2 +# Loading work.instruction_counter +# Loading work.rom +# Loading work.ram +# Loading work.control_unit +# Loading work.instruction_classifier +# Loading work.register_file +# Loading work.sign_extender +# Loading work.alu +# Loading work.asu +# Loading work.lu +# Loading work.seven_seg_4digit +# Loading work.seven_seg +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 +# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 +add wave -position end sim:/mips_tb/clk +add wave -position end sim:/mips_tb/num_errors +add wave -position end sim:/mips_tb/CPU/REGS/regs_out +add wave -position end sim:/mips_tb/CPU/REGS/regs +force -freeze sim:/mips_tb/clk 1 0, 0 {5 ps} -r 10 +run +# Beginning MIPS tests +# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[8] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[9] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[10] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[11] == 32'd14 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[12] == -32'sd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[14] == 32'd3 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[16] == 32'd2 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[17] == 32'd15 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[18] == 32'd13 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == -32'sd16 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[20] == 32'd1 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# All MIPS tests passing +quit -sim +# End time: 10:59:29 on Oct 16,2026, Elapsed time: 0:09:50 +# Errors: 0, Warnings: 13 +vsim work.ram +# vsim work.ram +# Start time: 10:59:43 on Oct 16,2026 +# Loading sv_std.std +# Loading work.ram +quit -sim +# End time: 10:59:51 on Oct 16,2026, Elapsed time: 0:00:08 # Errors: 0, Warnings: 1 +vsim work.mips_tb +# vsim work.mips_tb +# Start time: 10:59:55 on Oct 16,2026 +# Loading sv_std.std +# Loading work.mips_tb +# Loading work.assignment2 +# Loading work.instruction_counter +# Loading work.rom +# Loading work.ram +# Loading work.control_unit +# Loading work.instruction_classifier +# Loading work.register_file +# Loading work.sign_extender +# Loading work.alu +# Loading work.asu +# Loading work.lu +# Loading work.seven_seg_4digit +# Loading work.seven_seg +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. +# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 +# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 +# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). +# Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 +add wave -position end sim:/mips_tb/CPU/instruction +add wave -position end sim:/mips_tb/clk +add wave -position end sim:/mips_tb/CPU/clk +force -freeze sim:/mips_tb/clk 1 0, 0 {25 ps} -r 50 +force -freeze sim:/mips_tb/CPU/clk 1 0, 0 {25 ps} -r 50 +run +# Beginning MIPS tests +# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[0] == 32'(N) failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[8] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[9] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[10] == 32'd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[11] == 32'd14 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[12] == -32'sd7 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[13] == 32'd10 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[14] == 32'd3 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[16] == 32'd2 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[17] == 32'd15 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[18] == 32'd13 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[19] == -32'sd16 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# Check CPU.REGS.regs[20] == 32'd1 failed +# +# t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 +# +# All MIPS tests passing +# End time: 11:31:43 on Oct 16,2026, Elapsed time: 0:31:48 +# Errors: 0, Warnings: 13 diff --git a/ModelSim/vsim.wlf b/ModelSim/vsim.wlf index f25da77..d736fde 100644 Binary files a/ModelSim/vsim.wlf and b/ModelSim/vsim.wlf differ diff --git a/ModelSim/work/_info b/ModelSim/work/_info index e031d68..48be210 100644 --- a/ModelSim/work/_info +++ b/ModelSim/work/_info @@ -11,32 +11,32 @@ cModel Technology d/home/oliver/intelFPGA/20.1/modelsim_ase/bin valu Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3 -Z1 !s110 1789448641 +Z1 !s110 1792107153 !i10b 1 -!s100 Kh9ZlG?nRa:nnklUM3MaM0 +!s100 meV@F]8El[fjh_ULLA@iR2 Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1 -IlI`[:Ol82B@F8AM_FVkV41 +I<0ZXcWH[]FIo]cjVef19`2 Z3 VDg1SIo80bB@j0V0VzS_@n1 S1 Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim -Z5 w1789355084 +w1792036226 8alu.sv Falu.sv -!i122 18 -L0 9 28 -Z6 OV;L;2020.1;71 +!i122 90 +L0 9 31 +Z5 OV;L;2020.1;71 r1 !s85 0 31 -Z7 !s108 1789448641.000000 -Z8 !s107 lu.sv|asu.sv|alu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv| -Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv| +Z6 !s108 1792107152.000000 +Z7 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv| +Z8 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv| !i113 1 -Z10 o-work work -sv -Z11 tCvgOpt 0 +Z9 o-work work -sv +Z10 tCvgOpt 0 valu_tb R0 -R1 +Z11 !s110 1792107152 !i10b 1 !s100 8=>8o`KV]hRM]V8AV?S[C1 R2 @@ -44,74 +44,150 @@ Iz[VXe9HJ@koSDFNR185;i1 R3 S1 R4 -R5 +Z12 w1789355084 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv -!i122 18 +!i122 79 L0 3 214 -R6 +R5 r1 !s85 0 31 +R6 +!s107 lu.sv|asu.sv|alu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv| +!s90 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+8instruction_counter.sv +Finstruction_counter.sv +!i122 90 +L0 4 17 +R5 +r1 +!s85 0 +31 +R6 +R7 +R8 +!i113 1 +R9 R10 -R11 vlu R0 -Z17 !s110 1789449208 +R1 !i10b 1 !s100 H5AG9eSQKJkS4F`0;5hWl0 R2 @@ -169,24 +270,24 @@ IObN^<8?MCaP;K@UKCVaP^1 R3 S1 R4 -R5 +R14 8lu.sv Flu.sv -!i122 26 -Z18 L0 3 16 -R6 +!i122 90 +Z15 L0 3 16 +R5 r1 !s85 0 31 -Z19 !s108 1789449208.000000 -!s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| -Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| +R6 +R7 +R8 !i113 1 +R9 R10 -R11 vlu_tb R0 -R17 +R11 !i10b 1 !s100 AE_liX6DCD[3>b;K6Wgf72 R2 @@ -194,24 +295,124 @@ IC?h=m;SY77_D:GA0FRCL@TZ0g[C5g2 +R2 +ImO]Pc4zj;o69UAilj_VEd3 +R3 +S1 +R4 +w1792104861 +8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv +F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv +!i122 90 +L0 14 82 +R5 +r1 +!s85 0 +31 +R6 +R7 +R8 +!i113 1 +R9 +R10 +vram +R0 +R1 +!i10b 1 +!s100 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seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv| +!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv| +!i113 1 +R9 R10 -R11 vseven_seg_tb R0 -R22 +R1 !i10b 1 !s100 jPijM2]zTRBV8TFdD?Q`I1 R2 @@ -247,65 +473,90 @@ R4 w1788418794 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv -!i122 24 +!i122 96 L0 3 66 -R6 +R5 r1 !s85 0 31 -R23 -R24 -R25 +R16 +R17 +R18 !i113 1 +R9 R10 -R11 vshifter R0 -Z26 !s110 1789448794 +R1 !i10b 1 -!s100 clk[0].IN2 -HID_Register[0] => ~NO_FANOUT~ -HID_Register[1] => ~NO_FANOUT~ -HID_Register[2] => ~NO_FANOUT~ -HID_Register[3] => ~NO_FANOUT~ -HID_Register[4] => ~NO_FANOUT~ +HID_Register[0] => Mux0.IN4 +HID_Register[0] => Mux1.IN4 +HID_Register[0] => Mux2.IN4 +HID_Register[0] => Mux3.IN4 +HID_Register[0] => Mux4.IN4 +HID_Register[0] => Mux5.IN4 +HID_Register[0] => Mux6.IN4 +HID_Register[0] => Mux7.IN4 +HID_Register[0] => Mux8.IN4 +HID_Register[0] => Mux9.IN4 +HID_Register[0] => Mux10.IN4 +HID_Register[0] => Mux11.IN4 +HID_Register[0] => Mux12.IN4 +HID_Register[0] => Mux13.IN4 +HID_Register[0] => Mux14.IN4 +HID_Register[0] => Mux15.IN4 +HID_Register[0] => Mux16.IN4 +HID_Register[0] => Mux17.IN4 +HID_Register[0] => Mux18.IN4 +HID_Register[0] => Mux19.IN4 +HID_Register[0] => Mux20.IN4 +HID_Register[0] => Mux21.IN4 +HID_Register[0] => Mux22.IN4 +HID_Register[0] => Mux23.IN4 +HID_Register[0] => Mux24.IN4 +HID_Register[0] => Mux25.IN4 +HID_Register[0] => Mux26.IN4 +HID_Register[0] => Mux27.IN4 +HID_Register[0] => Mux28.IN4 +HID_Register[0] => Mux29.IN4 +HID_Register[0] => Mux30.IN4 +HID_Register[0] => Mux31.IN4 +HID_Register[1] => Mux0.IN3 +HID_Register[1] => Mux1.IN3 +HID_Register[1] => Mux2.IN3 +HID_Register[1] => Mux3.IN3 +HID_Register[1] => Mux4.IN3 +HID_Register[1] => Mux5.IN3 +HID_Register[1] => Mux6.IN3 +HID_Register[1] => Mux7.IN3 +HID_Register[1] => Mux8.IN3 +HID_Register[1] => Mux9.IN3 +HID_Register[1] => Mux10.IN3 +HID_Register[1] => Mux11.IN3 +HID_Register[1] => Mux12.IN3 +HID_Register[1] => Mux13.IN3 +HID_Register[1] => Mux14.IN3 +HID_Register[1] => Mux15.IN3 +HID_Register[1] => Mux16.IN3 +HID_Register[1] => Mux17.IN3 +HID_Register[1] => Mux18.IN3 +HID_Register[1] => Mux19.IN3 +HID_Register[1] => Mux20.IN3 +HID_Register[1] => Mux21.IN3 +HID_Register[1] => Mux22.IN3 +HID_Register[1] => Mux23.IN3 +HID_Register[1] => Mux24.IN3 +HID_Register[1] => Mux25.IN3 +HID_Register[1] => Mux26.IN3 +HID_Register[1] => Mux27.IN3 +HID_Register[1] => Mux28.IN3 +HID_Register[1] => Mux29.IN3 +HID_Register[1] => Mux30.IN3 +HID_Register[1] => Mux31.IN3 +HID_Register[2] => Mux0.IN2 +HID_Register[2] => Mux1.IN2 +HID_Register[2] => Mux2.IN2 +HID_Register[2] => Mux3.IN2 +HID_Register[2] => Mux4.IN2 +HID_Register[2] => Mux5.IN2 +HID_Register[2] => Mux6.IN2 +HID_Register[2] => Mux7.IN2 +HID_Register[2] => Mux8.IN2 +HID_Register[2] => Mux9.IN2 +HID_Register[2] => Mux10.IN2 +HID_Register[2] => Mux11.IN2 +HID_Register[2] => Mux12.IN2 +HID_Register[2] => Mux13.IN2 +HID_Register[2] => Mux14.IN2 +HID_Register[2] => Mux15.IN2 +HID_Register[2] => Mux16.IN2 +HID_Register[2] => Mux17.IN2 +HID_Register[2] => Mux18.IN2 +HID_Register[2] => Mux19.IN2 +HID_Register[2] => Mux20.IN2 +HID_Register[2] => Mux21.IN2 +HID_Register[2] => Mux22.IN2 +HID_Register[2] => Mux23.IN2 +HID_Register[2] => Mux24.IN2 +HID_Register[2] => Mux25.IN2 +HID_Register[2] => Mux26.IN2 +HID_Register[2] => Mux27.IN2 +HID_Register[2] => Mux28.IN2 +HID_Register[2] => Mux29.IN2 +HID_Register[2] => Mux30.IN2 +HID_Register[2] => Mux31.IN2 +HID_Register[3] => Mux0.IN1 +HID_Register[3] => Mux1.IN1 +HID_Register[3] => Mux2.IN1 +HID_Register[3] => Mux3.IN1 +HID_Register[3] => Mux4.IN1 +HID_Register[3] => Mux5.IN1 +HID_Register[3] => Mux6.IN1 +HID_Register[3] => Mux7.IN1 +HID_Register[3] => Mux8.IN1 +HID_Register[3] => Mux9.IN1 +HID_Register[3] => Mux10.IN1 +HID_Register[3] => Mux11.IN1 +HID_Register[3] => Mux12.IN1 +HID_Register[3] => Mux13.IN1 +HID_Register[3] => Mux14.IN1 +HID_Register[3] => Mux15.IN1 +HID_Register[3] => Mux16.IN1 +HID_Register[3] => Mux17.IN1 +HID_Register[3] => Mux18.IN1 +HID_Register[3] => Mux19.IN1 +HID_Register[3] => Mux20.IN1 +HID_Register[3] => Mux21.IN1 +HID_Register[3] => Mux22.IN1 +HID_Register[3] => Mux23.IN1 +HID_Register[3] => Mux24.IN1 +HID_Register[3] => Mux25.IN1 +HID_Register[3] => Mux26.IN1 +HID_Register[3] => Mux27.IN1 +HID_Register[3] => Mux28.IN1 +HID_Register[3] => Mux29.IN1 +HID_Register[3] => Mux30.IN1 +HID_Register[3] => Mux31.IN1 +HID_Register[4] => Mux0.IN0 +HID_Register[4] => Mux1.IN0 +HID_Register[4] => Mux2.IN0 +HID_Register[4] => Mux3.IN0 +HID_Register[4] => Mux4.IN0 +HID_Register[4] => Mux5.IN0 +HID_Register[4] => Mux6.IN0 +HID_Register[4] => Mux7.IN0 +HID_Register[4] => Mux8.IN0 +HID_Register[4] => Mux9.IN0 +HID_Register[4] => Mux10.IN0 +HID_Register[4] => Mux11.IN0 +HID_Register[4] => Mux12.IN0 +HID_Register[4] => Mux13.IN0 +HID_Register[4] => Mux14.IN0 +HID_Register[4] => Mux15.IN0 +HID_Register[4] => Mux16.IN0 +HID_Register[4] => Mux17.IN0 +HID_Register[4] => Mux18.IN0 +HID_Register[4] => Mux19.IN0 +HID_Register[4] => Mux20.IN0 +HID_Register[4] => Mux21.IN0 +HID_Register[4] => Mux22.IN0 +HID_Register[4] => Mux23.IN0 +HID_Register[4] => Mux24.IN0 +HID_Register[4] => Mux25.IN0 +HID_Register[4] => Mux26.IN0 +HID_Register[4] => Mux27.IN0 +HID_Register[4] => Mux28.IN0 +HID_Register[4] => Mux29.IN0 +HID_Register[4] => Mux30.IN0 +HID_Register[4] => Mux31.IN0 HID_PC[0] => ~NO_FANOUT~ -HID_Hi_Low[0] => ~NO_FANOUT~ +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT +HID_Hi_Low[0] => PC_Reg_Display.OUTPUTSELECT out_seg_0[0] << seven_seg_4digit:display.segments0 out_seg_0[1] << seven_seg_4digit:display.segments0 out_seg_0[2] << seven_seg_4digit:display.segments0 @@ -217,7 +387,652 @@ Dout[30] <= mem.DATAOUT30 Dout[31] <= mem.DATAOUT31 -|assignment2|instruction_classifier:INSTRUCTION_CLASSIFIER +|assignment2|ram:RAM +clk[0] => mem.we_a.CLK +clk[0] => mem.waddr_a[10].CLK +clk[0] => mem.waddr_a[9].CLK +clk[0] => mem.waddr_a[8].CLK +clk[0] => mem.waddr_a[7].CLK +clk[0] => mem.waddr_a[6].CLK +clk[0] => mem.waddr_a[5].CLK +clk[0] => mem.waddr_a[4].CLK +clk[0] => mem.waddr_a[3].CLK +clk[0] => mem.waddr_a[2].CLK +clk[0] => mem.waddr_a[1].CLK +clk[0] => mem.waddr_a[0].CLK +clk[0] => mem.data_a[-1].CLK +clk[0] => mem.data_a[0].CLK +clk[0] => mem.CLK0 +addr[0] => mem.waddr_a[0].DATAIN +addr[0] => mem.WADDR +addr[0] => mem.RADDR +addr[1] => mem.waddr_a[1].DATAIN +addr[1] => mem.WADDR1 +addr[1] => mem.RADDR1 +addr[2] => mem.waddr_a[2].DATAIN +addr[2] => mem.WADDR2 +addr[2] => mem.RADDR2 +addr[3] => mem.waddr_a[3].DATAIN +addr[3] => mem.WADDR3 +addr[3] => mem.RADDR3 +addr[4] => mem.waddr_a[4].DATAIN +addr[4] => mem.WADDR4 +addr[4] => mem.RADDR4 +addr[5] => mem.waddr_a[5].DATAIN +addr[5] => mem.WADDR5 +addr[5] => mem.RADDR5 +addr[6] => mem.waddr_a[6].DATAIN +addr[6] => mem.WADDR6 +addr[6] => mem.RADDR6 +addr[7] => mem.waddr_a[7].DATAIN +addr[7] => mem.WADDR7 +addr[7] => mem.RADDR7 +addr[8] => mem.waddr_a[8].DATAIN +addr[8] => mem.WADDR8 +addr[8] => mem.RADDR8 +addr[9] => mem.waddr_a[9].DATAIN +addr[9] => mem.WADDR9 +addr[9] => mem.RADDR9 +addr[10] => mem.waddr_a[10].DATAIN +addr[10] => mem.WADDR10 +addr[10] => mem.RADDR10 +addr[11] => ~NO_FANOUT~ +addr[12] => ~NO_FANOUT~ +addr[13] => ~NO_FANOUT~ +addr[14] => ~NO_FANOUT~ +addr[15] => ~NO_FANOUT~ +addr[16] => ~NO_FANOUT~ +addr[17] => ~NO_FANOUT~ +addr[18] => ~NO_FANOUT~ +addr[19] => ~NO_FANOUT~ +addr[20] => ~NO_FANOUT~ +addr[21] => ~NO_FANOUT~ +addr[22] => ~NO_FANOUT~ +addr[23] => ~NO_FANOUT~ +addr[24] => ~NO_FANOUT~ +addr[25] => ~NO_FANOUT~ +addr[26] => ~NO_FANOUT~ +addr[27] => ~NO_FANOUT~ +addr[28] => ~NO_FANOUT~ +addr[29] => ~NO_FANOUT~ +addr[30] => ~NO_FANOUT~ +addr[31] => ~NO_FANOUT~ +addr[32] => ~NO_FANOUT~ +addr[33] => ~NO_FANOUT~ +addr[34] => ~NO_FANOUT~ +addr[35] => ~NO_FANOUT~ +addr[36] => ~NO_FANOUT~ +addr[37] => ~NO_FANOUT~ +addr[38] => ~NO_FANOUT~ +addr[39] => ~NO_FANOUT~ +addr[40] => ~NO_FANOUT~ +addr[41] => ~NO_FANOUT~ +addr[42] => ~NO_FANOUT~ +addr[43] => ~NO_FANOUT~ +addr[44] => ~NO_FANOUT~ +addr[45] => ~NO_FANOUT~ +addr[46] => ~NO_FANOUT~ +addr[47] => ~NO_FANOUT~ +addr[48] => ~NO_FANOUT~ +addr[49] => ~NO_FANOUT~ +addr[50] => ~NO_FANOUT~ +addr[51] => ~NO_FANOUT~ +addr[52] => ~NO_FANOUT~ +addr[53] => ~NO_FANOUT~ +addr[54] => ~NO_FANOUT~ +addr[55] => ~NO_FANOUT~ +addr[56] => ~NO_FANOUT~ +addr[57] => ~NO_FANOUT~ +addr[58] => ~NO_FANOUT~ +addr[59] => ~NO_FANOUT~ +addr[60] => ~NO_FANOUT~ +addr[61] => ~NO_FANOUT~ +addr[62] => ~NO_FANOUT~ +addr[63] => ~NO_FANOUT~ +addr[64] => ~NO_FANOUT~ +addr[65] => ~NO_FANOUT~ +addr[66] => ~NO_FANOUT~ +addr[67] => ~NO_FANOUT~ +addr[68] => ~NO_FANOUT~ +addr[69] => ~NO_FANOUT~ +addr[70] => ~NO_FANOUT~ +addr[71] => ~NO_FANOUT~ +addr[72] => ~NO_FANOUT~ +addr[73] => ~NO_FANOUT~ +addr[74] => ~NO_FANOUT~ +addr[75] => ~NO_FANOUT~ +addr[76] => ~NO_FANOUT~ +addr[77] => ~NO_FANOUT~ +addr[78] => ~NO_FANOUT~ +addr[79] => ~NO_FANOUT~ +addr[80] => ~NO_FANOUT~ +addr[81] => ~NO_FANOUT~ +addr[82] => ~NO_FANOUT~ +addr[83] => ~NO_FANOUT~ +addr[84] => ~NO_FANOUT~ +addr[85] => ~NO_FANOUT~ +addr[86] => ~NO_FANOUT~ +addr[87] => ~NO_FANOUT~ +addr[88] => ~NO_FANOUT~ +addr[89] => ~NO_FANOUT~ +addr[90] => ~NO_FANOUT~ +addr[91] => ~NO_FANOUT~ +addr[92] => ~NO_FANOUT~ +addr[93] => ~NO_FANOUT~ +addr[94] => ~NO_FANOUT~ +addr[95] => ~NO_FANOUT~ +addr[96] => ~NO_FANOUT~ +addr[97] => ~NO_FANOUT~ +addr[98] => ~NO_FANOUT~ +addr[99] => ~NO_FANOUT~ +addr[100] => ~NO_FANOUT~ +addr[101] => ~NO_FANOUT~ +addr[102] => ~NO_FANOUT~ +addr[103] => ~NO_FANOUT~ +addr[104] => ~NO_FANOUT~ +addr[105] => ~NO_FANOUT~ +addr[106] => ~NO_FANOUT~ +addr[107] => ~NO_FANOUT~ +addr[108] => ~NO_FANOUT~ +addr[109] => ~NO_FANOUT~ +addr[110] => ~NO_FANOUT~ +addr[111] => ~NO_FANOUT~ +addr[112] => ~NO_FANOUT~ +addr[113] => ~NO_FANOUT~ +addr[114] => ~NO_FANOUT~ +addr[115] => ~NO_FANOUT~ +addr[116] => ~NO_FANOUT~ +addr[117] => ~NO_FANOUT~ +addr[118] => ~NO_FANOUT~ +addr[119] => ~NO_FANOUT~ +addr[120] => ~NO_FANOUT~ +addr[121] => ~NO_FANOUT~ +addr[122] => ~NO_FANOUT~ +addr[123] => ~NO_FANOUT~ +addr[124] => ~NO_FANOUT~ +addr[125] => ~NO_FANOUT~ +addr[126] => ~NO_FANOUT~ +addr[127] => ~NO_FANOUT~ +addr[128] => ~NO_FANOUT~ +addr[129] => ~NO_FANOUT~ +addr[130] => ~NO_FANOUT~ +addr[131] => ~NO_FANOUT~ +addr[132] => ~NO_FANOUT~ +addr[133] => ~NO_FANOUT~ +addr[134] => ~NO_FANOUT~ +addr[135] => ~NO_FANOUT~ +addr[136] => ~NO_FANOUT~ +addr[137] => ~NO_FANOUT~ +addr[138] => ~NO_FANOUT~ +addr[139] => ~NO_FANOUT~ +addr[140] => ~NO_FANOUT~ +addr[141] => ~NO_FANOUT~ +addr[142] => ~NO_FANOUT~ +addr[143] => ~NO_FANOUT~ +addr[144] => ~NO_FANOUT~ +addr[145] => ~NO_FANOUT~ +addr[146] => ~NO_FANOUT~ +addr[147] => ~NO_FANOUT~ +addr[148] => ~NO_FANOUT~ +addr[149] => ~NO_FANOUT~ +addr[150] => ~NO_FANOUT~ +addr[151] => ~NO_FANOUT~ +addr[152] => ~NO_FANOUT~ +addr[153] => ~NO_FANOUT~ +addr[154] => ~NO_FANOUT~ +addr[155] => ~NO_FANOUT~ +addr[156] => ~NO_FANOUT~ +addr[157] => ~NO_FANOUT~ +addr[158] => ~NO_FANOUT~ +addr[159] => ~NO_FANOUT~ +addr[160] => ~NO_FANOUT~ +addr[161] => ~NO_FANOUT~ +addr[162] => ~NO_FANOUT~ +addr[163] => ~NO_FANOUT~ +addr[164] => ~NO_FANOUT~ +addr[165] => ~NO_FANOUT~ +addr[166] => ~NO_FANOUT~ +addr[167] => ~NO_FANOUT~ +addr[168] => ~NO_FANOUT~ +addr[169] => ~NO_FANOUT~ +addr[170] => ~NO_FANOUT~ +addr[171] => ~NO_FANOUT~ +addr[172] => ~NO_FANOUT~ +addr[173] => ~NO_FANOUT~ +addr[174] => ~NO_FANOUT~ +addr[175] => ~NO_FANOUT~ +addr[176] => ~NO_FANOUT~ +addr[177] => ~NO_FANOUT~ +addr[178] => ~NO_FANOUT~ +addr[179] => ~NO_FANOUT~ +addr[180] => ~NO_FANOUT~ +addr[181] => ~NO_FANOUT~ +addr[182] => ~NO_FANOUT~ +addr[183] => ~NO_FANOUT~ +addr[184] => ~NO_FANOUT~ +addr[185] => ~NO_FANOUT~ +addr[186] => ~NO_FANOUT~ +addr[187] => ~NO_FANOUT~ +addr[188] => ~NO_FANOUT~ +addr[189] => ~NO_FANOUT~ +addr[190] => ~NO_FANOUT~ +addr[191] => ~NO_FANOUT~ +addr[192] => ~NO_FANOUT~ +addr[193] => ~NO_FANOUT~ +addr[194] => ~NO_FANOUT~ +addr[195] => ~NO_FANOUT~ +addr[196] => ~NO_FANOUT~ +addr[197] => ~NO_FANOUT~ +addr[198] => ~NO_FANOUT~ +addr[199] => ~NO_FANOUT~ +addr[200] => ~NO_FANOUT~ +addr[201] => ~NO_FANOUT~ +addr[202] => ~NO_FANOUT~ +addr[203] => ~NO_FANOUT~ +addr[204] => ~NO_FANOUT~ +addr[205] => ~NO_FANOUT~ +addr[206] => ~NO_FANOUT~ +addr[207] => ~NO_FANOUT~ +addr[208] => ~NO_FANOUT~ +addr[209] => ~NO_FANOUT~ +addr[210] => ~NO_FANOUT~ +addr[211] => ~NO_FANOUT~ +addr[212] => ~NO_FANOUT~ +addr[213] => ~NO_FANOUT~ +addr[214] => ~NO_FANOUT~ +addr[215] => ~NO_FANOUT~ +addr[216] => ~NO_FANOUT~ +addr[217] => ~NO_FANOUT~ +addr[218] => ~NO_FANOUT~ +addr[219] => ~NO_FANOUT~ +addr[220] => ~NO_FANOUT~ +addr[221] => ~NO_FANOUT~ +addr[222] => ~NO_FANOUT~ +addr[223] => ~NO_FANOUT~ +addr[224] => ~NO_FANOUT~ +addr[225] => ~NO_FANOUT~ +addr[226] => ~NO_FANOUT~ +addr[227] => ~NO_FANOUT~ +addr[228] => ~NO_FANOUT~ +addr[229] => ~NO_FANOUT~ +addr[230] => ~NO_FANOUT~ +addr[231] => ~NO_FANOUT~ +addr[232] => ~NO_FANOUT~ +addr[233] => ~NO_FANOUT~ +addr[234] => ~NO_FANOUT~ +addr[235] => ~NO_FANOUT~ +addr[236] => ~NO_FANOUT~ +addr[237] => ~NO_FANOUT~ +addr[238] => ~NO_FANOUT~ +addr[239] => ~NO_FANOUT~ +addr[240] => ~NO_FANOUT~ +addr[241] => ~NO_FANOUT~ +addr[242] => ~NO_FANOUT~ +addr[243] => ~NO_FANOUT~ +addr[244] => ~NO_FANOUT~ +addr[245] => ~NO_FANOUT~ +addr[246] => ~NO_FANOUT~ +addr[247] => ~NO_FANOUT~ +addr[248] => ~NO_FANOUT~ +addr[249] => ~NO_FANOUT~ +addr[250] => ~NO_FANOUT~ +addr[251] => ~NO_FANOUT~ +addr[252] => ~NO_FANOUT~ +addr[253] => ~NO_FANOUT~ +addr[254] => ~NO_FANOUT~ +addr[255] => ~NO_FANOUT~ +addr[256] => ~NO_FANOUT~ +addr[257] => ~NO_FANOUT~ +addr[258] => ~NO_FANOUT~ +addr[259] => ~NO_FANOUT~ +addr[260] => ~NO_FANOUT~ +addr[261] => ~NO_FANOUT~ +addr[262] => ~NO_FANOUT~ +addr[263] => ~NO_FANOUT~ +addr[264] => ~NO_FANOUT~ +addr[265] => ~NO_FANOUT~ +addr[266] => ~NO_FANOUT~ +addr[267] => ~NO_FANOUT~ +addr[268] => ~NO_FANOUT~ +addr[269] => ~NO_FANOUT~ +addr[270] => ~NO_FANOUT~ +addr[271] => ~NO_FANOUT~ +addr[272] => ~NO_FANOUT~ +addr[273] => ~NO_FANOUT~ +addr[274] => ~NO_FANOUT~ +addr[275] => ~NO_FANOUT~ +addr[276] => ~NO_FANOUT~ +addr[277] => ~NO_FANOUT~ +addr[278] => ~NO_FANOUT~ +addr[279] => ~NO_FANOUT~ +addr[280] => ~NO_FANOUT~ +addr[281] => ~NO_FANOUT~ +addr[282] => ~NO_FANOUT~ +addr[283] => ~NO_FANOUT~ +addr[284] => ~NO_FANOUT~ +addr[285] => ~NO_FANOUT~ +addr[286] => ~NO_FANOUT~ +addr[287] => ~NO_FANOUT~ +addr[288] => ~NO_FANOUT~ +addr[289] => ~NO_FANOUT~ +addr[290] => ~NO_FANOUT~ +addr[291] => ~NO_FANOUT~ +addr[292] => ~NO_FANOUT~ +addr[293] => ~NO_FANOUT~ +addr[294] => ~NO_FANOUT~ +addr[295] => ~NO_FANOUT~ +addr[296] => ~NO_FANOUT~ +addr[297] => ~NO_FANOUT~ +addr[298] => ~NO_FANOUT~ +addr[299] => ~NO_FANOUT~ +addr[300] => ~NO_FANOUT~ +addr[301] => ~NO_FANOUT~ +addr[302] => ~NO_FANOUT~ +addr[303] => ~NO_FANOUT~ +addr[304] => ~NO_FANOUT~ +addr[305] => ~NO_FANOUT~ +addr[306] => ~NO_FANOUT~ +addr[307] => ~NO_FANOUT~ +addr[308] => ~NO_FANOUT~ +addr[309] => ~NO_FANOUT~ +addr[310] => ~NO_FANOUT~ +addr[311] => ~NO_FANOUT~ +addr[312] => ~NO_FANOUT~ +addr[313] => ~NO_FANOUT~ +addr[314] => ~NO_FANOUT~ +addr[315] => ~NO_FANOUT~ +addr[316] => ~NO_FANOUT~ +addr[317] => ~NO_FANOUT~ +addr[318] => ~NO_FANOUT~ +addr[319] => ~NO_FANOUT~ +addr[320] => ~NO_FANOUT~ +addr[321] => ~NO_FANOUT~ +addr[322] => ~NO_FANOUT~ +addr[323] => ~NO_FANOUT~ +addr[324] => ~NO_FANOUT~ +addr[325] => ~NO_FANOUT~ +addr[326] => ~NO_FANOUT~ +addr[327] => ~NO_FANOUT~ +addr[328] => ~NO_FANOUT~ +addr[329] => ~NO_FANOUT~ +addr[330] => ~NO_FANOUT~ +addr[331] => ~NO_FANOUT~ +addr[332] => ~NO_FANOUT~ +addr[333] => ~NO_FANOUT~ +addr[334] => ~NO_FANOUT~ +addr[335] => ~NO_FANOUT~ +addr[336] => ~NO_FANOUT~ +addr[337] => ~NO_FANOUT~ +addr[338] => ~NO_FANOUT~ +addr[339] => ~NO_FANOUT~ +addr[340] => ~NO_FANOUT~ +addr[341] => ~NO_FANOUT~ +addr[342] => ~NO_FANOUT~ +addr[343] => ~NO_FANOUT~ +addr[344] => ~NO_FANOUT~ +addr[345] => ~NO_FANOUT~ +addr[346] => ~NO_FANOUT~ +addr[347] => ~NO_FANOUT~ +addr[348] => ~NO_FANOUT~ +addr[349] => ~NO_FANOUT~ +addr[350] => ~NO_FANOUT~ +addr[351] => ~NO_FANOUT~ +addr[352] => ~NO_FANOUT~ +addr[353] => ~NO_FANOUT~ +addr[354] => ~NO_FANOUT~ +addr[355] => ~NO_FANOUT~ +addr[356] => ~NO_FANOUT~ +addr[357] => ~NO_FANOUT~ +addr[358] => ~NO_FANOUT~ +addr[359] => ~NO_FANOUT~ +addr[360] => ~NO_FANOUT~ +addr[361] => ~NO_FANOUT~ +addr[362] => ~NO_FANOUT~ +addr[363] => ~NO_FANOUT~ +addr[364] => ~NO_FANOUT~ +addr[365] => ~NO_FANOUT~ +addr[366] => ~NO_FANOUT~ +addr[367] => ~NO_FANOUT~ +addr[368] => ~NO_FANOUT~ +addr[369] => ~NO_FANOUT~ +addr[370] => ~NO_FANOUT~ +addr[371] => ~NO_FANOUT~ +addr[372] => ~NO_FANOUT~ +addr[373] => ~NO_FANOUT~ +addr[374] => ~NO_FANOUT~ +addr[375] => ~NO_FANOUT~ +addr[376] => ~NO_FANOUT~ +addr[377] => ~NO_FANOUT~ +addr[378] => ~NO_FANOUT~ +addr[379] => ~NO_FANOUT~ +addr[380] => ~NO_FANOUT~ +addr[381] => ~NO_FANOUT~ +addr[382] => ~NO_FANOUT~ +addr[383] => ~NO_FANOUT~ +addr[384] => ~NO_FANOUT~ +addr[385] => ~NO_FANOUT~ +addr[386] => ~NO_FANOUT~ +addr[387] => ~NO_FANOUT~ +addr[388] => ~NO_FANOUT~ +addr[389] => ~NO_FANOUT~ +addr[390] => ~NO_FANOUT~ +addr[391] => ~NO_FANOUT~ +addr[392] => ~NO_FANOUT~ +addr[393] => ~NO_FANOUT~ +addr[394] => ~NO_FANOUT~ +addr[395] => ~NO_FANOUT~ +addr[396] => ~NO_FANOUT~ +addr[397] => ~NO_FANOUT~ +addr[398] => ~NO_FANOUT~ +addr[399] => ~NO_FANOUT~ +addr[400] => ~NO_FANOUT~ +addr[401] => ~NO_FANOUT~ +addr[402] => ~NO_FANOUT~ +addr[403] => ~NO_FANOUT~ +addr[404] => ~NO_FANOUT~ +addr[405] => ~NO_FANOUT~ +addr[406] => ~NO_FANOUT~ +addr[407] => ~NO_FANOUT~ +addr[408] => ~NO_FANOUT~ +addr[409] => ~NO_FANOUT~ +addr[410] => ~NO_FANOUT~ +addr[411] => ~NO_FANOUT~ +addr[412] => ~NO_FANOUT~ +addr[413] => ~NO_FANOUT~ +addr[414] => ~NO_FANOUT~ +addr[415] => ~NO_FANOUT~ +addr[416] => ~NO_FANOUT~ +addr[417] => ~NO_FANOUT~ +addr[418] => ~NO_FANOUT~ +addr[419] => ~NO_FANOUT~ +addr[420] => ~NO_FANOUT~ +addr[421] => ~NO_FANOUT~ +addr[422] => ~NO_FANOUT~ +addr[423] => ~NO_FANOUT~ +addr[424] => ~NO_FANOUT~ +addr[425] => ~NO_FANOUT~ +addr[426] => ~NO_FANOUT~ +addr[427] => ~NO_FANOUT~ +addr[428] => ~NO_FANOUT~ +addr[429] => ~NO_FANOUT~ +addr[430] => ~NO_FANOUT~ +addr[431] => ~NO_FANOUT~ +addr[432] => ~NO_FANOUT~ +addr[433] => ~NO_FANOUT~ +addr[434] => ~NO_FANOUT~ +addr[435] => ~NO_FANOUT~ +addr[436] => ~NO_FANOUT~ +addr[437] => ~NO_FANOUT~ +addr[438] => ~NO_FANOUT~ +addr[439] => ~NO_FANOUT~ +addr[440] => ~NO_FANOUT~ +addr[441] => ~NO_FANOUT~ +addr[442] => ~NO_FANOUT~ +addr[443] => ~NO_FANOUT~ +addr[444] => ~NO_FANOUT~ +addr[445] => ~NO_FANOUT~ +addr[446] => ~NO_FANOUT~ +addr[447] => ~NO_FANOUT~ +addr[448] => ~NO_FANOUT~ +addr[449] => ~NO_FANOUT~ +addr[450] => ~NO_FANOUT~ +addr[451] => ~NO_FANOUT~ +addr[452] => ~NO_FANOUT~ +addr[453] => ~NO_FANOUT~ +addr[454] => ~NO_FANOUT~ +addr[455] => ~NO_FANOUT~ +addr[456] => ~NO_FANOUT~ +addr[457] => ~NO_FANOUT~ +addr[458] => ~NO_FANOUT~ +addr[459] => ~NO_FANOUT~ +addr[460] => ~NO_FANOUT~ +addr[461] => ~NO_FANOUT~ +addr[462] => ~NO_FANOUT~ +addr[463] => ~NO_FANOUT~ +addr[464] => ~NO_FANOUT~ +addr[465] => ~NO_FANOUT~ +addr[466] => ~NO_FANOUT~ +addr[467] => ~NO_FANOUT~ +addr[468] => ~NO_FANOUT~ +addr[469] => ~NO_FANOUT~ +addr[470] => ~NO_FANOUT~ +addr[471] => ~NO_FANOUT~ +addr[472] => ~NO_FANOUT~ +addr[473] => ~NO_FANOUT~ +addr[474] => ~NO_FANOUT~ +addr[475] => ~NO_FANOUT~ +addr[476] => ~NO_FANOUT~ +addr[477] => ~NO_FANOUT~ +addr[478] => ~NO_FANOUT~ +addr[479] => ~NO_FANOUT~ +addr[480] => ~NO_FANOUT~ +addr[481] => ~NO_FANOUT~ +addr[482] => ~NO_FANOUT~ +addr[483] => ~NO_FANOUT~ +addr[484] => ~NO_FANOUT~ +addr[485] => ~NO_FANOUT~ +addr[486] => ~NO_FANOUT~ +addr[487] => ~NO_FANOUT~ +addr[488] => ~NO_FANOUT~ +addr[489] => ~NO_FANOUT~ +addr[490] => ~NO_FANOUT~ +addr[491] => ~NO_FANOUT~ +addr[492] => ~NO_FANOUT~ +addr[493] => ~NO_FANOUT~ +addr[494] => ~NO_FANOUT~ +addr[495] => ~NO_FANOUT~ +addr[496] => ~NO_FANOUT~ +addr[497] => ~NO_FANOUT~ +addr[498] => ~NO_FANOUT~ +addr[499] => ~NO_FANOUT~ +addr[500] => ~NO_FANOUT~ +addr[501] => ~NO_FANOUT~ +addr[502] => ~NO_FANOUT~ +addr[503] => ~NO_FANOUT~ +addr[504] => ~NO_FANOUT~ +addr[505] => ~NO_FANOUT~ +addr[506] => ~NO_FANOUT~ +addr[507] => ~NO_FANOUT~ +addr[508] => ~NO_FANOUT~ +addr[509] => ~NO_FANOUT~ +addr[510] => ~NO_FANOUT~ +addr[511] => ~NO_FANOUT~ +we[0] => mem.we_a.DATAIN +we[0] => mem.WE +data_in[0] => mem.data_a[0].DATAIN +data_in[0] => mem.DATAIN +data_in[1] => mem.data_a[-1].DATAIN +data_in[1] => mem.DATAIN1 +data_in[2] => ~NO_FANOUT~ +data_in[3] => ~NO_FANOUT~ +data_in[4] => ~NO_FANOUT~ +data_in[5] => ~NO_FANOUT~ +data_in[6] => ~NO_FANOUT~ +data_in[7] => ~NO_FANOUT~ +data_in[8] => ~NO_FANOUT~ +data_in[9] => ~NO_FANOUT~ +data_in[10] => ~NO_FANOUT~ +data_in[11] => ~NO_FANOUT~ +data_in[12] => ~NO_FANOUT~ +data_in[13] => ~NO_FANOUT~ +data_in[14] => ~NO_FANOUT~ +data_in[15] => ~NO_FANOUT~ +data_in[16] => ~NO_FANOUT~ +data_in[17] => ~NO_FANOUT~ +data_in[18] => ~NO_FANOUT~ +data_in[19] => ~NO_FANOUT~ +data_in[20] => ~NO_FANOUT~ +data_in[21] => ~NO_FANOUT~ +data_in[22] => ~NO_FANOUT~ +data_in[23] => ~NO_FANOUT~ +data_in[24] => ~NO_FANOUT~ +data_in[25] => ~NO_FANOUT~ +data_in[26] => ~NO_FANOUT~ +data_in[27] => ~NO_FANOUT~ +data_in[28] => ~NO_FANOUT~ +data_in[29] => ~NO_FANOUT~ +data_in[30] => ~NO_FANOUT~ +data_in[31] => ~NO_FANOUT~ +data_out[0] <= mem.DATAOUT +data_out[1] <= mem.DATAOUT1 +data_out[2] <= +data_out[3] <= +data_out[4] <= +data_out[5] <= +data_out[6] <= +data_out[7] <= +data_out[8] <= +data_out[9] <= +data_out[10] <= +data_out[11] <= +data_out[12] <= +data_out[13] <= +data_out[14] <= +data_out[15] <= +data_out[16] <= +data_out[17] <= +data_out[18] <= +data_out[19] <= +data_out[20] <= +data_out[21] <= +data_out[22] <= +data_out[23] <= +data_out[24] <= +data_out[25] <= +data_out[26] <= +data_out[27] <= +data_out[28] <= +data_out[29] <= +data_out[30] <= +data_out[31] <= + + +|assignment2|control_unit:CONTROL_UNIT +op[0] => op[0].IN1 +op[1] => op[1].IN1 +op[2] => op[2].IN1 +op[3] => op[3].IN1 +op[4] => op[4].IN1 +op[5] => op[5].IN1 +func[0] => ALU_FN.IN1 +func[1] => ALU_FN.IN1 +func[2] => ALU_FN.IN1 +func[3] => ALU_FN.IN1 +func[4] => ~NO_FANOUT~ +func[5] => ~NO_FANOUT~ +M2R[0] <= M2R.DB_MAX_OUTPUT_PORT_TYPE +M2W[0] <= M2W.DB_MAX_OUTPUT_PORT_TYPE +B[0] <= B.DB_MAX_OUTPUT_PORT_TYPE +ALU_FN[0] <= ALU_FN.DB_MAX_OUTPUT_PORT_TYPE +ALU_FN[1] <= ALU_FN.DB_MAX_OUTPUT_PORT_TYPE +ALU_FN[2] <= ALU_FN.DB_MAX_OUTPUT_PORT_TYPE +ALU_FN[3] <= ALU_FN.DB_MAX_OUTPUT_PORT_TYPE +ALU_SRC[0] <= ALU_SRC.DB_MAX_OUTPUT_PORT_TYPE +RDST[0] <= instruction_classifier:CLASSIFIER.port5 +RW[0] <= RW.DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|control_unit:CONTROL_UNIT|instruction_classifier:CLASSIFIER op[0] => Equal0.IN5 op[0] => Equal1.IN0 op[1] => Equal0.IN4 @@ -254,216 +1069,3529 @@ F[0] <= Equal5.DB_MAX_OUTPUT_PORT_TYPE M[0] <= op[5].DB_MAX_OUTPUT_PORT_TYPE -|assignment2|instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER -op[0] => Equal0.IN2 -op[0] => Equal1.IN0 -op[1] => Equal0.IN1 -op[1] => Equal1.IN2 -op[1] => Equal2.IN0 -op[2] => en_alu.DATAIN -op[2] => Equal0.IN0 -op[2] => Equal1.IN1 -op[2] => Equal2.IN1 -en_shifter <= Equal0.DB_MAX_OUTPUT_PORT_TYPE -en_jmp <= Equal1.DB_MAX_OUTPUT_PORT_TYPE -en_mul <= Equal2.DB_MAX_OUTPUT_PORT_TYPE -en_alu <= op[2].DB_MAX_OUTPUT_PORT_TYPE - - |assignment2|register_file:REGS -clk[0] => regs.we_a.CLK -clk[0] => regs.waddr_a[4].CLK -clk[0] => regs.waddr_a[3].CLK -clk[0] => regs.waddr_a[2].CLK -clk[0] => regs.waddr_a[1].CLK -clk[0] => regs.waddr_a[0].CLK -clk[0] => regs.data_a[31].CLK -clk[0] => regs.data_a[30].CLK -clk[0] => regs.data_a[29].CLK -clk[0] => regs.data_a[28].CLK -clk[0] => regs.data_a[27].CLK -clk[0] => regs.data_a[26].CLK -clk[0] => regs.data_a[25].CLK -clk[0] => regs.data_a[24].CLK -clk[0] => regs.data_a[23].CLK -clk[0] => regs.data_a[22].CLK -clk[0] => regs.data_a[21].CLK -clk[0] => regs.data_a[20].CLK -clk[0] => regs.data_a[19].CLK -clk[0] => regs.data_a[18].CLK -clk[0] => regs.data_a[17].CLK -clk[0] => regs.data_a[16].CLK -clk[0] => regs.data_a[15].CLK -clk[0] => regs.data_a[14].CLK -clk[0] => regs.data_a[13].CLK -clk[0] => regs.data_a[12].CLK -clk[0] => regs.data_a[11].CLK -clk[0] => regs.data_a[10].CLK -clk[0] => regs.data_a[9].CLK -clk[0] => regs.data_a[8].CLK -clk[0] => regs.data_a[7].CLK -clk[0] => regs.data_a[6].CLK -clk[0] => regs.data_a[5].CLK -clk[0] => regs.data_a[4].CLK -clk[0] => regs.data_a[3].CLK -clk[0] => regs.data_a[2].CLK -clk[0] => regs.data_a[1].CLK -clk[0] => regs.data_a[0].CLK -clk[0] => regs.CLK0 +clk[0] => regs[31][0].CLK +clk[0] => regs[31][1].CLK +clk[0] => regs[31][2].CLK +clk[0] => regs[31][3].CLK +clk[0] => regs[31][4].CLK +clk[0] => regs[31][5].CLK +clk[0] => regs[31][6].CLK +clk[0] => regs[31][7].CLK +clk[0] => regs[31][8].CLK +clk[0] => regs[31][9].CLK +clk[0] => regs[31][10].CLK +clk[0] => regs[31][11].CLK +clk[0] => regs[31][12].CLK +clk[0] => regs[31][13].CLK +clk[0] => regs[31][14].CLK +clk[0] => regs[31][15].CLK +clk[0] => regs[31][16].CLK +clk[0] => regs[31][17].CLK +clk[0] => regs[31][18].CLK +clk[0] => regs[31][19].CLK +clk[0] => regs[31][20].CLK +clk[0] => regs[31][21].CLK +clk[0] => regs[31][22].CLK +clk[0] => regs[31][23].CLK +clk[0] => regs[31][24].CLK +clk[0] => regs[31][25].CLK +clk[0] => regs[31][26].CLK +clk[0] => regs[31][27].CLK +clk[0] => regs[31][28].CLK +clk[0] => regs[31][29].CLK +clk[0] => regs[31][30].CLK +clk[0] => regs[31][31].CLK +clk[0] => regs[30][0].CLK +clk[0] => regs[30][1].CLK +clk[0] => regs[30][2].CLK +clk[0] => regs[30][3].CLK +clk[0] => regs[30][4].CLK +clk[0] => regs[30][5].CLK +clk[0] => regs[30][6].CLK +clk[0] => regs[30][7].CLK +clk[0] => regs[30][8].CLK +clk[0] => regs[30][9].CLK +clk[0] => regs[30][10].CLK +clk[0] => regs[30][11].CLK +clk[0] => regs[30][12].CLK +clk[0] => regs[30][13].CLK +clk[0] => regs[30][14].CLK +clk[0] => regs[30][15].CLK +clk[0] => regs[30][16].CLK +clk[0] => regs[30][17].CLK +clk[0] => regs[30][18].CLK +clk[0] => regs[30][19].CLK +clk[0] => regs[30][20].CLK +clk[0] => regs[30][21].CLK +clk[0] => regs[30][22].CLK +clk[0] => regs[30][23].CLK +clk[0] => regs[30][24].CLK +clk[0] => regs[30][25].CLK +clk[0] => regs[30][26].CLK +clk[0] => regs[30][27].CLK +clk[0] => regs[30][28].CLK +clk[0] => regs[30][29].CLK +clk[0] => regs[30][30].CLK +clk[0] => regs[30][31].CLK +clk[0] => regs[29][0].CLK +clk[0] => regs[29][1].CLK +clk[0] => regs[29][2].CLK +clk[0] => regs[29][3].CLK +clk[0] => regs[29][4].CLK +clk[0] => regs[29][5].CLK +clk[0] => regs[29][6].CLK +clk[0] => regs[29][7].CLK +clk[0] => regs[29][8].CLK +clk[0] => regs[29][9].CLK +clk[0] => regs[29][10].CLK +clk[0] => regs[29][11].CLK +clk[0] => regs[29][12].CLK +clk[0] => regs[29][13].CLK +clk[0] => regs[29][14].CLK +clk[0] => regs[29][15].CLK +clk[0] => regs[29][16].CLK +clk[0] => regs[29][17].CLK +clk[0] => regs[29][18].CLK +clk[0] => regs[29][19].CLK +clk[0] => regs[29][20].CLK +clk[0] => regs[29][21].CLK +clk[0] => regs[29][22].CLK +clk[0] => regs[29][23].CLK +clk[0] => regs[29][24].CLK +clk[0] => regs[29][25].CLK +clk[0] => regs[29][26].CLK +clk[0] => regs[29][27].CLK +clk[0] => regs[29][28].CLK +clk[0] => regs[29][29].CLK +clk[0] => regs[29][30].CLK +clk[0] => regs[29][31].CLK +clk[0] => regs[28][0].CLK +clk[0] => regs[28][1].CLK +clk[0] => regs[28][2].CLK +clk[0] => regs[28][3].CLK +clk[0] => regs[28][4].CLK +clk[0] => regs[28][5].CLK +clk[0] => regs[28][6].CLK +clk[0] => regs[28][7].CLK +clk[0] => regs[28][8].CLK +clk[0] => regs[28][9].CLK +clk[0] => regs[28][10].CLK +clk[0] => regs[28][11].CLK +clk[0] => regs[28][12].CLK +clk[0] => regs[28][13].CLK +clk[0] => regs[28][14].CLK +clk[0] => regs[28][15].CLK +clk[0] => regs[28][16].CLK +clk[0] => regs[28][17].CLK +clk[0] => regs[28][18].CLK +clk[0] => regs[28][19].CLK +clk[0] => regs[28][20].CLK +clk[0] => regs[28][21].CLK +clk[0] => regs[28][22].CLK +clk[0] => regs[28][23].CLK +clk[0] => regs[28][24].CLK +clk[0] => regs[28][25].CLK +clk[0] => regs[28][26].CLK +clk[0] => regs[28][27].CLK +clk[0] => regs[28][28].CLK +clk[0] => regs[28][29].CLK +clk[0] => regs[28][30].CLK +clk[0] => regs[28][31].CLK +clk[0] => regs[27][0].CLK +clk[0] => regs[27][1].CLK +clk[0] => regs[27][2].CLK +clk[0] => regs[27][3].CLK +clk[0] => regs[27][4].CLK +clk[0] => regs[27][5].CLK +clk[0] => regs[27][6].CLK +clk[0] => regs[27][7].CLK +clk[0] => regs[27][8].CLK +clk[0] => regs[27][9].CLK +clk[0] => regs[27][10].CLK +clk[0] => regs[27][11].CLK +clk[0] => regs[27][12].CLK +clk[0] => regs[27][13].CLK +clk[0] => regs[27][14].CLK +clk[0] => regs[27][15].CLK +clk[0] => regs[27][16].CLK +clk[0] => regs[27][17].CLK +clk[0] => regs[27][18].CLK +clk[0] => regs[27][19].CLK +clk[0] => regs[27][20].CLK +clk[0] => regs[27][21].CLK +clk[0] => regs[27][22].CLK +clk[0] => regs[27][23].CLK +clk[0] => regs[27][24].CLK +clk[0] => regs[27][25].CLK +clk[0] => regs[27][26].CLK +clk[0] => regs[27][27].CLK +clk[0] => regs[27][28].CLK +clk[0] => regs[27][29].CLK +clk[0] => regs[27][30].CLK +clk[0] => regs[27][31].CLK +clk[0] => regs[26][0].CLK +clk[0] => regs[26][1].CLK +clk[0] => regs[26][2].CLK +clk[0] => regs[26][3].CLK +clk[0] => regs[26][4].CLK +clk[0] => regs[26][5].CLK +clk[0] => regs[26][6].CLK +clk[0] => regs[26][7].CLK +clk[0] => regs[26][8].CLK +clk[0] => regs[26][9].CLK +clk[0] => regs[26][10].CLK +clk[0] => regs[26][11].CLK +clk[0] => regs[26][12].CLK +clk[0] => regs[26][13].CLK +clk[0] => regs[26][14].CLK +clk[0] => regs[26][15].CLK +clk[0] => regs[26][16].CLK +clk[0] => regs[26][17].CLK +clk[0] => regs[26][18].CLK +clk[0] => regs[26][19].CLK +clk[0] => regs[26][20].CLK +clk[0] => regs[26][21].CLK +clk[0] => regs[26][22].CLK +clk[0] => regs[26][23].CLK +clk[0] => regs[26][24].CLK +clk[0] => regs[26][25].CLK +clk[0] => regs[26][26].CLK +clk[0] => regs[26][27].CLK +clk[0] => regs[26][28].CLK +clk[0] => regs[26][29].CLK +clk[0] => regs[26][30].CLK +clk[0] => regs[26][31].CLK +clk[0] => regs[25][0].CLK +clk[0] => regs[25][1].CLK +clk[0] => regs[25][2].CLK +clk[0] => regs[25][3].CLK +clk[0] => regs[25][4].CLK +clk[0] => regs[25][5].CLK +clk[0] => regs[25][6].CLK +clk[0] => regs[25][7].CLK +clk[0] => regs[25][8].CLK +clk[0] => regs[25][9].CLK +clk[0] => regs[25][10].CLK +clk[0] => regs[25][11].CLK +clk[0] => regs[25][12].CLK +clk[0] => regs[25][13].CLK +clk[0] => regs[25][14].CLK +clk[0] => regs[25][15].CLK +clk[0] => regs[25][16].CLK +clk[0] => regs[25][17].CLK +clk[0] => regs[25][18].CLK +clk[0] => regs[25][19].CLK +clk[0] => regs[25][20].CLK +clk[0] => regs[25][21].CLK +clk[0] => regs[25][22].CLK +clk[0] => regs[25][23].CLK +clk[0] => regs[25][24].CLK +clk[0] => regs[25][25].CLK +clk[0] => regs[25][26].CLK +clk[0] => regs[25][27].CLK +clk[0] => regs[25][28].CLK +clk[0] => regs[25][29].CLK +clk[0] => regs[25][30].CLK +clk[0] => regs[25][31].CLK +clk[0] => regs[24][0].CLK +clk[0] => regs[24][1].CLK +clk[0] => regs[24][2].CLK +clk[0] => regs[24][3].CLK +clk[0] => regs[24][4].CLK +clk[0] => regs[24][5].CLK +clk[0] => regs[24][6].CLK +clk[0] => regs[24][7].CLK +clk[0] => regs[24][8].CLK +clk[0] => regs[24][9].CLK +clk[0] => regs[24][10].CLK +clk[0] => regs[24][11].CLK +clk[0] => regs[24][12].CLK +clk[0] => regs[24][13].CLK +clk[0] => regs[24][14].CLK +clk[0] => regs[24][15].CLK +clk[0] => regs[24][16].CLK +clk[0] => regs[24][17].CLK +clk[0] => regs[24][18].CLK +clk[0] => regs[24][19].CLK +clk[0] => regs[24][20].CLK +clk[0] => regs[24][21].CLK +clk[0] => regs[24][22].CLK +clk[0] => regs[24][23].CLK +clk[0] => regs[24][24].CLK +clk[0] => regs[24][25].CLK +clk[0] => regs[24][26].CLK +clk[0] => regs[24][27].CLK +clk[0] => regs[24][28].CLK +clk[0] => regs[24][29].CLK +clk[0] => regs[24][30].CLK +clk[0] => regs[24][31].CLK +clk[0] => regs[23][0].CLK +clk[0] => regs[23][1].CLK +clk[0] => regs[23][2].CLK +clk[0] => regs[23][3].CLK +clk[0] => regs[23][4].CLK +clk[0] => regs[23][5].CLK +clk[0] => regs[23][6].CLK +clk[0] => regs[23][7].CLK +clk[0] => regs[23][8].CLK +clk[0] => regs[23][9].CLK +clk[0] => regs[23][10].CLK +clk[0] => regs[23][11].CLK +clk[0] => regs[23][12].CLK +clk[0] => regs[23][13].CLK +clk[0] => regs[23][14].CLK +clk[0] => regs[23][15].CLK +clk[0] => regs[23][16].CLK +clk[0] => regs[23][17].CLK +clk[0] => regs[23][18].CLK +clk[0] => regs[23][19].CLK +clk[0] => regs[23][20].CLK +clk[0] => regs[23][21].CLK +clk[0] => regs[23][22].CLK +clk[0] => regs[23][23].CLK +clk[0] => regs[23][24].CLK +clk[0] => regs[23][25].CLK +clk[0] => regs[23][26].CLK +clk[0] => regs[23][27].CLK +clk[0] => regs[23][28].CLK +clk[0] => regs[23][29].CLK +clk[0] => regs[23][30].CLK +clk[0] => regs[23][31].CLK +clk[0] => regs[22][0].CLK +clk[0] => regs[22][1].CLK +clk[0] => regs[22][2].CLK +clk[0] => regs[22][3].CLK +clk[0] => regs[22][4].CLK +clk[0] => regs[22][5].CLK +clk[0] => regs[22][6].CLK +clk[0] => regs[22][7].CLK +clk[0] => regs[22][8].CLK +clk[0] => regs[22][9].CLK +clk[0] => regs[22][10].CLK +clk[0] => regs[22][11].CLK +clk[0] => regs[22][12].CLK +clk[0] => regs[22][13].CLK +clk[0] => regs[22][14].CLK +clk[0] => regs[22][15].CLK +clk[0] => regs[22][16].CLK +clk[0] => regs[22][17].CLK +clk[0] => regs[22][18].CLK +clk[0] => regs[22][19].CLK +clk[0] => regs[22][20].CLK +clk[0] => regs[22][21].CLK +clk[0] => regs[22][22].CLK +clk[0] => regs[22][23].CLK +clk[0] => regs[22][24].CLK +clk[0] => regs[22][25].CLK +clk[0] => regs[22][26].CLK +clk[0] => regs[22][27].CLK +clk[0] => regs[22][28].CLK +clk[0] => regs[22][29].CLK +clk[0] => regs[22][30].CLK +clk[0] => regs[22][31].CLK +clk[0] => regs[21][0].CLK +clk[0] => regs[21][1].CLK +clk[0] => regs[21][2].CLK +clk[0] => regs[21][3].CLK +clk[0] => regs[21][4].CLK +clk[0] => regs[21][5].CLK +clk[0] => regs[21][6].CLK +clk[0] => regs[21][7].CLK +clk[0] => regs[21][8].CLK +clk[0] => regs[21][9].CLK +clk[0] => regs[21][10].CLK +clk[0] => regs[21][11].CLK +clk[0] => regs[21][12].CLK +clk[0] => regs[21][13].CLK +clk[0] => regs[21][14].CLK +clk[0] => regs[21][15].CLK +clk[0] => regs[21][16].CLK +clk[0] => regs[21][17].CLK +clk[0] => regs[21][18].CLK +clk[0] => regs[21][19].CLK +clk[0] => regs[21][20].CLK +clk[0] => regs[21][21].CLK +clk[0] => regs[21][22].CLK +clk[0] => regs[21][23].CLK +clk[0] => regs[21][24].CLK +clk[0] => regs[21][25].CLK +clk[0] => regs[21][26].CLK +clk[0] => regs[21][27].CLK +clk[0] => regs[21][28].CLK +clk[0] => regs[21][29].CLK +clk[0] => regs[21][30].CLK +clk[0] => regs[21][31].CLK +clk[0] => regs[20][0].CLK +clk[0] => regs[20][1].CLK +clk[0] => regs[20][2].CLK +clk[0] => regs[20][3].CLK +clk[0] => regs[20][4].CLK +clk[0] => regs[20][5].CLK +clk[0] => regs[20][6].CLK +clk[0] => regs[20][7].CLK +clk[0] => regs[20][8].CLK +clk[0] => regs[20][9].CLK +clk[0] => regs[20][10].CLK +clk[0] => regs[20][11].CLK +clk[0] => regs[20][12].CLK +clk[0] => regs[20][13].CLK +clk[0] => regs[20][14].CLK +clk[0] => regs[20][15].CLK +clk[0] => regs[20][16].CLK +clk[0] => regs[20][17].CLK +clk[0] => regs[20][18].CLK +clk[0] => regs[20][19].CLK +clk[0] => regs[20][20].CLK +clk[0] => regs[20][21].CLK +clk[0] => regs[20][22].CLK +clk[0] => regs[20][23].CLK +clk[0] => regs[20][24].CLK +clk[0] => regs[20][25].CLK +clk[0] => regs[20][26].CLK +clk[0] => regs[20][27].CLK +clk[0] => regs[20][28].CLK +clk[0] => regs[20][29].CLK +clk[0] => regs[20][30].CLK +clk[0] => regs[20][31].CLK +clk[0] => regs[19][0].CLK +clk[0] => regs[19][1].CLK +clk[0] => regs[19][2].CLK +clk[0] => regs[19][3].CLK +clk[0] => regs[19][4].CLK +clk[0] => regs[19][5].CLK +clk[0] => regs[19][6].CLK +clk[0] => regs[19][7].CLK +clk[0] => regs[19][8].CLK +clk[0] => regs[19][9].CLK +clk[0] => regs[19][10].CLK +clk[0] => regs[19][11].CLK +clk[0] => regs[19][12].CLK +clk[0] => regs[19][13].CLK +clk[0] => regs[19][14].CLK +clk[0] => regs[19][15].CLK +clk[0] => regs[19][16].CLK +clk[0] => regs[19][17].CLK +clk[0] => regs[19][18].CLK +clk[0] => regs[19][19].CLK +clk[0] => regs[19][20].CLK +clk[0] => regs[19][21].CLK +clk[0] => regs[19][22].CLK +clk[0] => regs[19][23].CLK +clk[0] => regs[19][24].CLK +clk[0] => regs[19][25].CLK +clk[0] => regs[19][26].CLK +clk[0] => regs[19][27].CLK +clk[0] => regs[19][28].CLK +clk[0] => regs[19][29].CLK +clk[0] => regs[19][30].CLK +clk[0] => regs[19][31].CLK +clk[0] => regs[18][0].CLK +clk[0] => regs[18][1].CLK +clk[0] => regs[18][2].CLK +clk[0] => regs[18][3].CLK +clk[0] => regs[18][4].CLK +clk[0] => regs[18][5].CLK +clk[0] => regs[18][6].CLK +clk[0] => regs[18][7].CLK +clk[0] => regs[18][8].CLK +clk[0] => regs[18][9].CLK +clk[0] => regs[18][10].CLK +clk[0] => regs[18][11].CLK +clk[0] => regs[18][12].CLK +clk[0] => regs[18][13].CLK +clk[0] => regs[18][14].CLK +clk[0] => regs[18][15].CLK +clk[0] => regs[18][16].CLK +clk[0] => regs[18][17].CLK +clk[0] => regs[18][18].CLK +clk[0] => regs[18][19].CLK +clk[0] => regs[18][20].CLK +clk[0] => regs[18][21].CLK +clk[0] => regs[18][22].CLK +clk[0] => regs[18][23].CLK +clk[0] => regs[18][24].CLK +clk[0] => regs[18][25].CLK +clk[0] => regs[18][26].CLK +clk[0] => regs[18][27].CLK +clk[0] => regs[18][28].CLK +clk[0] => regs[18][29].CLK +clk[0] => regs[18][30].CLK +clk[0] => regs[18][31].CLK +clk[0] => regs[17][0].CLK +clk[0] => regs[17][1].CLK +clk[0] => regs[17][2].CLK +clk[0] => regs[17][3].CLK +clk[0] => regs[17][4].CLK +clk[0] => regs[17][5].CLK +clk[0] => regs[17][6].CLK +clk[0] => regs[17][7].CLK +clk[0] => regs[17][8].CLK +clk[0] => regs[17][9].CLK +clk[0] => regs[17][10].CLK +clk[0] => regs[17][11].CLK +clk[0] => regs[17][12].CLK +clk[0] => regs[17][13].CLK +clk[0] => regs[17][14].CLK +clk[0] => regs[17][15].CLK +clk[0] => regs[17][16].CLK +clk[0] => regs[17][17].CLK +clk[0] => regs[17][18].CLK +clk[0] => regs[17][19].CLK +clk[0] => regs[17][20].CLK +clk[0] => regs[17][21].CLK +clk[0] => regs[17][22].CLK +clk[0] => regs[17][23].CLK +clk[0] => regs[17][24].CLK +clk[0] => regs[17][25].CLK +clk[0] => regs[17][26].CLK +clk[0] => regs[17][27].CLK +clk[0] => regs[17][28].CLK +clk[0] => regs[17][29].CLK +clk[0] => regs[17][30].CLK +clk[0] => regs[17][31].CLK +clk[0] => regs[16][0].CLK +clk[0] => regs[16][1].CLK +clk[0] => regs[16][2].CLK +clk[0] => regs[16][3].CLK +clk[0] => regs[16][4].CLK +clk[0] => regs[16][5].CLK +clk[0] => regs[16][6].CLK +clk[0] => regs[16][7].CLK +clk[0] => regs[16][8].CLK +clk[0] => regs[16][9].CLK +clk[0] => regs[16][10].CLK +clk[0] => regs[16][11].CLK +clk[0] => regs[16][12].CLK +clk[0] => regs[16][13].CLK +clk[0] => regs[16][14].CLK +clk[0] => regs[16][15].CLK +clk[0] => regs[16][16].CLK +clk[0] => regs[16][17].CLK +clk[0] => regs[16][18].CLK +clk[0] => regs[16][19].CLK +clk[0] => regs[16][20].CLK +clk[0] => regs[16][21].CLK +clk[0] => regs[16][22].CLK +clk[0] => regs[16][23].CLK +clk[0] => regs[16][24].CLK +clk[0] => regs[16][25].CLK +clk[0] => regs[16][26].CLK +clk[0] => regs[16][27].CLK +clk[0] => regs[16][28].CLK +clk[0] => regs[16][29].CLK +clk[0] => regs[16][30].CLK +clk[0] => regs[16][31].CLK +clk[0] => regs[15][0].CLK +clk[0] => regs[15][1].CLK +clk[0] => regs[15][2].CLK +clk[0] => regs[15][3].CLK +clk[0] => regs[15][4].CLK +clk[0] => regs[15][5].CLK +clk[0] => regs[15][6].CLK +clk[0] => regs[15][7].CLK +clk[0] => regs[15][8].CLK +clk[0] => regs[15][9].CLK +clk[0] => regs[15][10].CLK +clk[0] => regs[15][11].CLK +clk[0] => regs[15][12].CLK +clk[0] => regs[15][13].CLK +clk[0] => regs[15][14].CLK +clk[0] => regs[15][15].CLK +clk[0] => regs[15][16].CLK +clk[0] => regs[15][17].CLK +clk[0] => regs[15][18].CLK +clk[0] => regs[15][19].CLK +clk[0] => regs[15][20].CLK +clk[0] => regs[15][21].CLK +clk[0] => regs[15][22].CLK +clk[0] => regs[15][23].CLK +clk[0] => regs[15][24].CLK +clk[0] => regs[15][25].CLK +clk[0] => regs[15][26].CLK +clk[0] => regs[15][27].CLK +clk[0] => regs[15][28].CLK +clk[0] => regs[15][29].CLK +clk[0] => regs[15][30].CLK +clk[0] => regs[15][31].CLK +clk[0] => regs[14][0].CLK +clk[0] => regs[14][1].CLK +clk[0] => regs[14][2].CLK +clk[0] => regs[14][3].CLK +clk[0] => regs[14][4].CLK +clk[0] => regs[14][5].CLK +clk[0] => regs[14][6].CLK +clk[0] => regs[14][7].CLK +clk[0] => regs[14][8].CLK +clk[0] => regs[14][9].CLK +clk[0] => regs[14][10].CLK +clk[0] => regs[14][11].CLK +clk[0] => regs[14][12].CLK +clk[0] => regs[14][13].CLK +clk[0] => regs[14][14].CLK +clk[0] => regs[14][15].CLK +clk[0] => regs[14][16].CLK +clk[0] => regs[14][17].CLK +clk[0] => regs[14][18].CLK +clk[0] => regs[14][19].CLK +clk[0] => regs[14][20].CLK +clk[0] => regs[14][21].CLK +clk[0] => regs[14][22].CLK +clk[0] => regs[14][23].CLK +clk[0] => regs[14][24].CLK +clk[0] => regs[14][25].CLK +clk[0] => regs[14][26].CLK +clk[0] => regs[14][27].CLK +clk[0] => regs[14][28].CLK +clk[0] => regs[14][29].CLK +clk[0] => regs[14][30].CLK +clk[0] => regs[14][31].CLK +clk[0] => regs[13][0].CLK +clk[0] => regs[13][1].CLK +clk[0] => regs[13][2].CLK +clk[0] => regs[13][3].CLK +clk[0] => regs[13][4].CLK +clk[0] => regs[13][5].CLK +clk[0] => regs[13][6].CLK +clk[0] => regs[13][7].CLK +clk[0] => regs[13][8].CLK +clk[0] => regs[13][9].CLK +clk[0] => regs[13][10].CLK +clk[0] => regs[13][11].CLK +clk[0] => regs[13][12].CLK +clk[0] => regs[13][13].CLK +clk[0] => regs[13][14].CLK +clk[0] => regs[13][15].CLK +clk[0] => regs[13][16].CLK +clk[0] => regs[13][17].CLK +clk[0] => regs[13][18].CLK +clk[0] => regs[13][19].CLK +clk[0] => regs[13][20].CLK +clk[0] => regs[13][21].CLK +clk[0] => regs[13][22].CLK +clk[0] => regs[13][23].CLK +clk[0] => regs[13][24].CLK +clk[0] => regs[13][25].CLK +clk[0] => regs[13][26].CLK +clk[0] => regs[13][27].CLK +clk[0] => regs[13][28].CLK +clk[0] => regs[13][29].CLK +clk[0] => regs[13][30].CLK +clk[0] => regs[13][31].CLK +clk[0] => regs[12][0].CLK +clk[0] => regs[12][1].CLK +clk[0] => regs[12][2].CLK +clk[0] => regs[12][3].CLK +clk[0] => regs[12][4].CLK +clk[0] => regs[12][5].CLK +clk[0] => regs[12][6].CLK +clk[0] => regs[12][7].CLK +clk[0] => regs[12][8].CLK +clk[0] => regs[12][9].CLK +clk[0] => regs[12][10].CLK +clk[0] => regs[12][11].CLK +clk[0] => regs[12][12].CLK +clk[0] => regs[12][13].CLK +clk[0] => regs[12][14].CLK +clk[0] => regs[12][15].CLK +clk[0] => regs[12][16].CLK +clk[0] => regs[12][17].CLK +clk[0] => regs[12][18].CLK +clk[0] => regs[12][19].CLK +clk[0] => regs[12][20].CLK +clk[0] => regs[12][21].CLK +clk[0] => regs[12][22].CLK +clk[0] => regs[12][23].CLK +clk[0] => regs[12][24].CLK +clk[0] => regs[12][25].CLK +clk[0] => regs[12][26].CLK +clk[0] => regs[12][27].CLK +clk[0] => regs[12][28].CLK +clk[0] => regs[12][29].CLK +clk[0] => regs[12][30].CLK +clk[0] => regs[12][31].CLK +clk[0] => regs[11][0].CLK +clk[0] => regs[11][1].CLK +clk[0] => regs[11][2].CLK +clk[0] => regs[11][3].CLK +clk[0] => regs[11][4].CLK +clk[0] => regs[11][5].CLK +clk[0] => regs[11][6].CLK +clk[0] => regs[11][7].CLK +clk[0] => regs[11][8].CLK +clk[0] => regs[11][9].CLK +clk[0] => regs[11][10].CLK +clk[0] => regs[11][11].CLK +clk[0] => regs[11][12].CLK +clk[0] => regs[11][13].CLK +clk[0] => regs[11][14].CLK +clk[0] => regs[11][15].CLK +clk[0] => regs[11][16].CLK +clk[0] => regs[11][17].CLK +clk[0] => regs[11][18].CLK +clk[0] => regs[11][19].CLK +clk[0] => regs[11][20].CLK +clk[0] => regs[11][21].CLK +clk[0] => regs[11][22].CLK +clk[0] => regs[11][23].CLK +clk[0] => regs[11][24].CLK +clk[0] => regs[11][25].CLK +clk[0] => regs[11][26].CLK +clk[0] => regs[11][27].CLK +clk[0] => regs[11][28].CLK +clk[0] => regs[11][29].CLK +clk[0] => regs[11][30].CLK +clk[0] => regs[11][31].CLK +clk[0] => regs[10][0].CLK +clk[0] => regs[10][1].CLK +clk[0] => regs[10][2].CLK +clk[0] => regs[10][3].CLK +clk[0] => regs[10][4].CLK +clk[0] => regs[10][5].CLK +clk[0] => regs[10][6].CLK +clk[0] => regs[10][7].CLK +clk[0] => regs[10][8].CLK +clk[0] => regs[10][9].CLK +clk[0] => regs[10][10].CLK +clk[0] => regs[10][11].CLK +clk[0] => regs[10][12].CLK +clk[0] => regs[10][13].CLK +clk[0] => regs[10][14].CLK +clk[0] => regs[10][15].CLK +clk[0] => regs[10][16].CLK +clk[0] => regs[10][17].CLK +clk[0] => regs[10][18].CLK +clk[0] => regs[10][19].CLK +clk[0] => regs[10][20].CLK +clk[0] => regs[10][21].CLK +clk[0] => regs[10][22].CLK +clk[0] => regs[10][23].CLK +clk[0] => regs[10][24].CLK +clk[0] => regs[10][25].CLK +clk[0] => regs[10][26].CLK +clk[0] => regs[10][27].CLK +clk[0] => regs[10][28].CLK +clk[0] => regs[10][29].CLK +clk[0] => regs[10][30].CLK +clk[0] => regs[10][31].CLK +clk[0] => regs[9][0].CLK +clk[0] => regs[9][1].CLK +clk[0] => regs[9][2].CLK +clk[0] => regs[9][3].CLK +clk[0] => regs[9][4].CLK +clk[0] => regs[9][5].CLK +clk[0] => regs[9][6].CLK +clk[0] => regs[9][7].CLK +clk[0] => regs[9][8].CLK +clk[0] => regs[9][9].CLK +clk[0] => regs[9][10].CLK +clk[0] => regs[9][11].CLK +clk[0] => regs[9][12].CLK +clk[0] => regs[9][13].CLK +clk[0] => regs[9][14].CLK +clk[0] => regs[9][15].CLK +clk[0] => regs[9][16].CLK +clk[0] => regs[9][17].CLK +clk[0] => regs[9][18].CLK +clk[0] => regs[9][19].CLK +clk[0] => regs[9][20].CLK +clk[0] => regs[9][21].CLK +clk[0] => regs[9][22].CLK +clk[0] => regs[9][23].CLK +clk[0] => regs[9][24].CLK +clk[0] => regs[9][25].CLK +clk[0] => regs[9][26].CLK +clk[0] => regs[9][27].CLK +clk[0] => regs[9][28].CLK +clk[0] => regs[9][29].CLK +clk[0] => regs[9][30].CLK +clk[0] => regs[9][31].CLK +clk[0] => regs[8][0].CLK +clk[0] => regs[8][1].CLK +clk[0] => regs[8][2].CLK +clk[0] => regs[8][3].CLK +clk[0] => regs[8][4].CLK +clk[0] => regs[8][5].CLK +clk[0] => regs[8][6].CLK +clk[0] => regs[8][7].CLK +clk[0] => regs[8][8].CLK +clk[0] => regs[8][9].CLK +clk[0] => regs[8][10].CLK +clk[0] => regs[8][11].CLK +clk[0] => regs[8][12].CLK +clk[0] => regs[8][13].CLK +clk[0] => regs[8][14].CLK +clk[0] => regs[8][15].CLK +clk[0] => regs[8][16].CLK +clk[0] => regs[8][17].CLK +clk[0] => regs[8][18].CLK +clk[0] => regs[8][19].CLK +clk[0] => regs[8][20].CLK +clk[0] => regs[8][21].CLK +clk[0] => regs[8][22].CLK +clk[0] => regs[8][23].CLK +clk[0] => regs[8][24].CLK +clk[0] => regs[8][25].CLK +clk[0] => regs[8][26].CLK +clk[0] => regs[8][27].CLK +clk[0] => regs[8][28].CLK +clk[0] => regs[8][29].CLK +clk[0] => regs[8][30].CLK +clk[0] => regs[8][31].CLK +clk[0] => regs[7][0].CLK +clk[0] => regs[7][1].CLK +clk[0] => regs[7][2].CLK +clk[0] => regs[7][3].CLK +clk[0] => regs[7][4].CLK +clk[0] => regs[7][5].CLK +clk[0] => regs[7][6].CLK +clk[0] => regs[7][7].CLK +clk[0] => regs[7][8].CLK +clk[0] => regs[7][9].CLK +clk[0] => regs[7][10].CLK +clk[0] => regs[7][11].CLK +clk[0] => regs[7][12].CLK +clk[0] => regs[7][13].CLK +clk[0] => regs[7][14].CLK +clk[0] => regs[7][15].CLK +clk[0] => regs[7][16].CLK +clk[0] => regs[7][17].CLK +clk[0] => regs[7][18].CLK +clk[0] => regs[7][19].CLK +clk[0] => regs[7][20].CLK +clk[0] => regs[7][21].CLK +clk[0] => regs[7][22].CLK +clk[0] => regs[7][23].CLK +clk[0] => regs[7][24].CLK +clk[0] => regs[7][25].CLK +clk[0] => regs[7][26].CLK +clk[0] => regs[7][27].CLK +clk[0] => regs[7][28].CLK +clk[0] => regs[7][29].CLK +clk[0] => regs[7][30].CLK +clk[0] => regs[7][31].CLK +clk[0] => regs[6][0].CLK +clk[0] => regs[6][1].CLK +clk[0] => regs[6][2].CLK +clk[0] => regs[6][3].CLK +clk[0] => regs[6][4].CLK +clk[0] => regs[6][5].CLK +clk[0] => regs[6][6].CLK +clk[0] => regs[6][7].CLK +clk[0] => regs[6][8].CLK +clk[0] => regs[6][9].CLK +clk[0] => regs[6][10].CLK +clk[0] => regs[6][11].CLK +clk[0] => regs[6][12].CLK +clk[0] => regs[6][13].CLK +clk[0] => regs[6][14].CLK +clk[0] => regs[6][15].CLK +clk[0] => regs[6][16].CLK +clk[0] => regs[6][17].CLK +clk[0] => regs[6][18].CLK +clk[0] => regs[6][19].CLK +clk[0] => regs[6][20].CLK +clk[0] => regs[6][21].CLK +clk[0] => regs[6][22].CLK +clk[0] => regs[6][23].CLK +clk[0] => regs[6][24].CLK +clk[0] => regs[6][25].CLK +clk[0] => regs[6][26].CLK +clk[0] => regs[6][27].CLK +clk[0] => regs[6][28].CLK +clk[0] => regs[6][29].CLK +clk[0] => regs[6][30].CLK +clk[0] => regs[6][31].CLK +clk[0] => regs[5][0].CLK +clk[0] => regs[5][1].CLK +clk[0] => regs[5][2].CLK +clk[0] => regs[5][3].CLK +clk[0] => regs[5][4].CLK +clk[0] => regs[5][5].CLK +clk[0] => regs[5][6].CLK +clk[0] => regs[5][7].CLK +clk[0] => regs[5][8].CLK +clk[0] => regs[5][9].CLK +clk[0] => regs[5][10].CLK +clk[0] => regs[5][11].CLK +clk[0] => regs[5][12].CLK +clk[0] => regs[5][13].CLK +clk[0] => regs[5][14].CLK +clk[0] => regs[5][15].CLK +clk[0] => regs[5][16].CLK +clk[0] => regs[5][17].CLK +clk[0] => regs[5][18].CLK +clk[0] => regs[5][19].CLK +clk[0] => regs[5][20].CLK +clk[0] => regs[5][21].CLK +clk[0] => regs[5][22].CLK +clk[0] => regs[5][23].CLK +clk[0] => regs[5][24].CLK +clk[0] => regs[5][25].CLK +clk[0] => regs[5][26].CLK +clk[0] => regs[5][27].CLK +clk[0] => regs[5][28].CLK +clk[0] => regs[5][29].CLK +clk[0] => regs[5][30].CLK +clk[0] => regs[5][31].CLK +clk[0] => regs[4][0].CLK +clk[0] => regs[4][1].CLK +clk[0] => regs[4][2].CLK +clk[0] => regs[4][3].CLK +clk[0] => regs[4][4].CLK +clk[0] => regs[4][5].CLK +clk[0] => regs[4][6].CLK +clk[0] => regs[4][7].CLK +clk[0] => regs[4][8].CLK +clk[0] => regs[4][9].CLK +clk[0] => regs[4][10].CLK +clk[0] => regs[4][11].CLK +clk[0] => regs[4][12].CLK +clk[0] => regs[4][13].CLK +clk[0] => regs[4][14].CLK +clk[0] => regs[4][15].CLK +clk[0] => regs[4][16].CLK +clk[0] => regs[4][17].CLK +clk[0] => regs[4][18].CLK +clk[0] => regs[4][19].CLK +clk[0] => regs[4][20].CLK +clk[0] => regs[4][21].CLK +clk[0] => regs[4][22].CLK +clk[0] => regs[4][23].CLK +clk[0] => regs[4][24].CLK +clk[0] => regs[4][25].CLK +clk[0] => regs[4][26].CLK +clk[0] => regs[4][27].CLK +clk[0] => regs[4][28].CLK +clk[0] => regs[4][29].CLK +clk[0] => regs[4][30].CLK +clk[0] => regs[4][31].CLK +clk[0] => regs[3][0].CLK +clk[0] => regs[3][1].CLK +clk[0] => regs[3][2].CLK +clk[0] => regs[3][3].CLK +clk[0] => regs[3][4].CLK +clk[0] => regs[3][5].CLK +clk[0] => regs[3][6].CLK +clk[0] => regs[3][7].CLK +clk[0] => regs[3][8].CLK +clk[0] => regs[3][9].CLK +clk[0] => regs[3][10].CLK +clk[0] => regs[3][11].CLK +clk[0] => regs[3][12].CLK +clk[0] => regs[3][13].CLK +clk[0] => regs[3][14].CLK +clk[0] => regs[3][15].CLK +clk[0] => regs[3][16].CLK +clk[0] => regs[3][17].CLK +clk[0] => regs[3][18].CLK +clk[0] => regs[3][19].CLK +clk[0] => regs[3][20].CLK +clk[0] => regs[3][21].CLK +clk[0] => regs[3][22].CLK +clk[0] => regs[3][23].CLK +clk[0] => regs[3][24].CLK +clk[0] => regs[3][25].CLK +clk[0] => regs[3][26].CLK +clk[0] => regs[3][27].CLK +clk[0] => regs[3][28].CLK +clk[0] => regs[3][29].CLK +clk[0] => regs[3][30].CLK +clk[0] => regs[3][31].CLK +clk[0] => regs[2][0].CLK +clk[0] => regs[2][1].CLK +clk[0] => regs[2][2].CLK +clk[0] => regs[2][3].CLK +clk[0] => regs[2][4].CLK +clk[0] => regs[2][5].CLK +clk[0] => regs[2][6].CLK +clk[0] => regs[2][7].CLK +clk[0] => regs[2][8].CLK +clk[0] => regs[2][9].CLK +clk[0] => regs[2][10].CLK +clk[0] => regs[2][11].CLK +clk[0] => regs[2][12].CLK +clk[0] => regs[2][13].CLK +clk[0] => regs[2][14].CLK +clk[0] => regs[2][15].CLK +clk[0] => regs[2][16].CLK +clk[0] => regs[2][17].CLK +clk[0] => regs[2][18].CLK +clk[0] => regs[2][19].CLK +clk[0] => regs[2][20].CLK +clk[0] => regs[2][21].CLK +clk[0] => regs[2][22].CLK +clk[0] => regs[2][23].CLK +clk[0] => regs[2][24].CLK +clk[0] => regs[2][25].CLK +clk[0] => regs[2][26].CLK +clk[0] => regs[2][27].CLK +clk[0] => regs[2][28].CLK +clk[0] => regs[2][29].CLK +clk[0] => regs[2][30].CLK +clk[0] => regs[2][31].CLK +clk[0] => regs[1][0].CLK +clk[0] => regs[1][1].CLK +clk[0] => regs[1][2].CLK +clk[0] => regs[1][3].CLK +clk[0] => regs[1][4].CLK +clk[0] => regs[1][5].CLK +clk[0] => regs[1][6].CLK +clk[0] => regs[1][7].CLK +clk[0] => regs[1][8].CLK +clk[0] => regs[1][9].CLK +clk[0] => regs[1][10].CLK +clk[0] => regs[1][11].CLK +clk[0] => regs[1][12].CLK +clk[0] => regs[1][13].CLK +clk[0] => regs[1][14].CLK +clk[0] => regs[1][15].CLK +clk[0] => regs[1][16].CLK +clk[0] => regs[1][17].CLK +clk[0] => regs[1][18].CLK +clk[0] => regs[1][19].CLK +clk[0] => regs[1][20].CLK +clk[0] => regs[1][21].CLK +clk[0] => regs[1][22].CLK +clk[0] => regs[1][23].CLK +clk[0] => regs[1][24].CLK +clk[0] => regs[1][25].CLK +clk[0] => regs[1][26].CLK +clk[0] => regs[1][27].CLK +clk[0] => regs[1][28].CLK +clk[0] => regs[1][29].CLK +clk[0] => regs[1][30].CLK +clk[0] => regs[1][31].CLK +clk[0] => regs[0][0].CLK +clk[0] => regs[0][1].CLK +clk[0] => regs[0][2].CLK +clk[0] => regs[0][3].CLK +clk[0] => regs[0][4].CLK +clk[0] => regs[0][5].CLK +clk[0] => regs[0][6].CLK +clk[0] => regs[0][7].CLK +clk[0] => regs[0][8].CLK +clk[0] => regs[0][9].CLK +clk[0] => regs[0][10].CLK +clk[0] => regs[0][11].CLK +clk[0] => regs[0][12].CLK +clk[0] => regs[0][13].CLK +clk[0] => regs[0][14].CLK +clk[0] => regs[0][15].CLK +clk[0] => regs[0][16].CLK +clk[0] => regs[0][17].CLK +clk[0] => regs[0][18].CLK +clk[0] => regs[0][19].CLK +clk[0] => regs[0][20].CLK +clk[0] => regs[0][21].CLK +clk[0] => regs[0][22].CLK +clk[0] => regs[0][23].CLK +clk[0] => regs[0][24].CLK +clk[0] => regs[0][25].CLK +clk[0] => regs[0][26].CLK +clk[0] => regs[0][27].CLK +clk[0] => regs[0][28].CLK +clk[0] => regs[0][29].CLK +clk[0] => regs[0][30].CLK +clk[0] => regs[0][31].CLK we[0] => always0.IN1 -WA[0] => regs.waddr_a[0].DATAIN +WA[0] => Decoder0.IN4 WA[0] => Equal0.IN31 -WA[0] => regs.WADDR -WA[1] => regs.waddr_a[1].DATAIN +WA[1] => Decoder0.IN3 WA[1] => Equal0.IN30 -WA[1] => regs.WADDR1 -WA[2] => regs.waddr_a[2].DATAIN +WA[2] => Decoder0.IN2 WA[2] => Equal0.IN29 -WA[2] => regs.WADDR2 -WA[3] => regs.waddr_a[3].DATAIN +WA[3] => Decoder0.IN1 WA[3] => Equal0.IN28 -WA[3] => regs.WADDR3 -WA[4] => regs.waddr_a[4].DATAIN +WA[4] => Decoder0.IN0 WA[4] => Equal0.IN27 -WA[4] => regs.WADDR4 -WD[0] => regs.data_a[0].DATAIN -WD[0] => regs.DATAIN -WD[1] => regs.data_a[1].DATAIN -WD[1] => regs.DATAIN1 -WD[2] => regs.data_a[2].DATAIN -WD[2] => regs.DATAIN2 -WD[3] => regs.data_a[3].DATAIN -WD[3] => regs.DATAIN3 -WD[4] => regs.data_a[4].DATAIN -WD[4] => regs.DATAIN4 -WD[5] => regs.data_a[5].DATAIN -WD[5] => regs.DATAIN5 -WD[6] => regs.data_a[6].DATAIN -WD[6] => regs.DATAIN6 -WD[7] => regs.data_a[7].DATAIN -WD[7] => regs.DATAIN7 -WD[8] => regs.data_a[8].DATAIN -WD[8] => regs.DATAIN8 -WD[9] => regs.data_a[9].DATAIN -WD[9] => regs.DATAIN9 -WD[10] => regs.data_a[10].DATAIN -WD[10] => regs.DATAIN10 -WD[11] => regs.data_a[11].DATAIN -WD[11] => regs.DATAIN11 -WD[12] => regs.data_a[12].DATAIN -WD[12] => regs.DATAIN12 -WD[13] => regs.data_a[13].DATAIN -WD[13] => regs.DATAIN13 -WD[14] => regs.data_a[14].DATAIN -WD[14] => regs.DATAIN14 -WD[15] => regs.data_a[15].DATAIN -WD[15] => regs.DATAIN15 -WD[16] => regs.data_a[16].DATAIN -WD[16] => regs.DATAIN16 -WD[17] => regs.data_a[17].DATAIN -WD[17] => regs.DATAIN17 -WD[18] => regs.data_a[18].DATAIN -WD[18] => regs.DATAIN18 -WD[19] => regs.data_a[19].DATAIN -WD[19] => regs.DATAIN19 -WD[20] => regs.data_a[20].DATAIN -WD[20] => regs.DATAIN20 -WD[21] => regs.data_a[21].DATAIN -WD[21] => regs.DATAIN21 -WD[22] => regs.data_a[22].DATAIN -WD[22] => regs.DATAIN22 -WD[23] => regs.data_a[23].DATAIN -WD[23] => regs.DATAIN23 -WD[24] => regs.data_a[24].DATAIN -WD[24] => regs.DATAIN24 -WD[25] => regs.data_a[25].DATAIN -WD[25] => regs.DATAIN25 -WD[26] => regs.data_a[26].DATAIN -WD[26] => regs.DATAIN26 -WD[27] => regs.data_a[27].DATAIN -WD[27] => regs.DATAIN27 -WD[28] => regs.data_a[28].DATAIN -WD[28] => regs.DATAIN28 -WD[29] => regs.data_a[29].DATAIN -WD[29] => regs.DATAIN29 -WD[30] => regs.data_a[30].DATAIN -WD[30] => regs.DATAIN30 -WD[31] => regs.data_a[31].DATAIN -WD[31] => regs.DATAIN31 -RA1[0] => regs.RADDR -RA1[1] => regs.RADDR1 -RA1[2] => regs.RADDR2 -RA1[3] => regs.RADDR3 -RA1[4] => regs.RADDR4 -RD1[0] <= regs.DATAOUT -RD1[1] <= regs.DATAOUT1 -RD1[2] <= regs.DATAOUT2 -RD1[3] <= regs.DATAOUT3 -RD1[4] <= regs.DATAOUT4 -RD1[5] <= regs.DATAOUT5 -RD1[6] <= regs.DATAOUT6 -RD1[7] <= regs.DATAOUT7 -RD1[8] <= regs.DATAOUT8 -RD1[9] <= regs.DATAOUT9 -RD1[10] <= regs.DATAOUT10 -RD1[11] <= regs.DATAOUT11 -RD1[12] <= regs.DATAOUT12 -RD1[13] <= regs.DATAOUT13 -RD1[14] <= regs.DATAOUT14 -RD1[15] <= regs.DATAOUT15 -RD1[16] <= regs.DATAOUT16 -RD1[17] <= regs.DATAOUT17 -RD1[18] <= regs.DATAOUT18 -RD1[19] <= regs.DATAOUT19 -RD1[20] <= regs.DATAOUT20 -RD1[21] <= regs.DATAOUT21 -RD1[22] <= regs.DATAOUT22 -RD1[23] <= regs.DATAOUT23 -RD1[24] <= regs.DATAOUT24 -RD1[25] <= regs.DATAOUT25 -RD1[26] <= regs.DATAOUT26 -RD1[27] <= regs.DATAOUT27 -RD1[28] <= regs.DATAOUT28 -RD1[29] <= regs.DATAOUT29 -RD1[30] <= regs.DATAOUT30 -RD1[31] <= regs.DATAOUT31 -RA2[0] => regs.PORTBRADDR -RA2[1] => regs.PORTBRADDR1 -RA2[2] => regs.PORTBRADDR2 -RA2[3] => regs.PORTBRADDR3 -RA2[4] => regs.PORTBRADDR4 -RD2[0] <= regs.PORTBDATAOUT -RD2[1] <= regs.PORTBDATAOUT1 -RD2[2] <= regs.PORTBDATAOUT2 -RD2[3] <= regs.PORTBDATAOUT3 -RD2[4] <= regs.PORTBDATAOUT4 -RD2[5] <= regs.PORTBDATAOUT5 -RD2[6] <= regs.PORTBDATAOUT6 -RD2[7] <= regs.PORTBDATAOUT7 -RD2[8] <= regs.PORTBDATAOUT8 -RD2[9] <= regs.PORTBDATAOUT9 -RD2[10] <= regs.PORTBDATAOUT10 -RD2[11] <= regs.PORTBDATAOUT11 -RD2[12] <= regs.PORTBDATAOUT12 -RD2[13] <= regs.PORTBDATAOUT13 -RD2[14] <= regs.PORTBDATAOUT14 -RD2[15] <= regs.PORTBDATAOUT15 -RD2[16] <= regs.PORTBDATAOUT16 -RD2[17] <= regs.PORTBDATAOUT17 -RD2[18] <= regs.PORTBDATAOUT18 -RD2[19] <= regs.PORTBDATAOUT19 -RD2[20] <= regs.PORTBDATAOUT20 -RD2[21] <= regs.PORTBDATAOUT21 -RD2[22] <= regs.PORTBDATAOUT22 -RD2[23] <= regs.PORTBDATAOUT23 -RD2[24] <= regs.PORTBDATAOUT24 -RD2[25] <= regs.PORTBDATAOUT25 -RD2[26] <= regs.PORTBDATAOUT26 -RD2[27] <= regs.PORTBDATAOUT27 -RD2[28] <= regs.PORTBDATAOUT28 -RD2[29] <= regs.PORTBDATAOUT29 -RD2[30] <= regs.PORTBDATAOUT30 -RD2[31] <= regs.PORTBDATAOUT31 +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[0] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[1] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[2] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[3] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[4] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[5] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[6] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[7] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[8] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[9] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[10] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[11] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[12] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[13] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[14] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[15] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[16] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[17] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[18] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[19] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[20] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[21] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[22] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[23] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[24] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[25] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[26] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[27] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[28] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[29] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[30] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +WD[31] => regs.DATAB +RA1[0] => Mux0.IN4 +RA1[0] => Mux1.IN4 +RA1[0] => Mux2.IN4 +RA1[0] => Mux3.IN4 +RA1[0] => Mux4.IN4 +RA1[0] => Mux5.IN4 +RA1[0] => Mux6.IN4 +RA1[0] => Mux7.IN4 +RA1[0] => Mux8.IN4 +RA1[0] => Mux9.IN4 +RA1[0] => Mux10.IN4 +RA1[0] => Mux11.IN4 +RA1[0] => Mux12.IN4 +RA1[0] => Mux13.IN4 +RA1[0] => Mux14.IN4 +RA1[0] => Mux15.IN4 +RA1[0] => Mux16.IN4 +RA1[0] => Mux17.IN4 +RA1[0] => Mux18.IN4 +RA1[0] => Mux19.IN4 +RA1[0] => Mux20.IN4 +RA1[0] => Mux21.IN4 +RA1[0] => Mux22.IN4 +RA1[0] => Mux23.IN4 +RA1[0] => Mux24.IN4 +RA1[0] => Mux25.IN4 +RA1[0] => Mux26.IN4 +RA1[0] => Mux27.IN4 +RA1[0] => Mux28.IN4 +RA1[0] => Mux29.IN4 +RA1[0] => Mux30.IN4 +RA1[0] => Mux31.IN4 +RA1[1] => Mux0.IN3 +RA1[1] => Mux1.IN3 +RA1[1] => Mux2.IN3 +RA1[1] => Mux3.IN3 +RA1[1] => Mux4.IN3 +RA1[1] => Mux5.IN3 +RA1[1] => Mux6.IN3 +RA1[1] => Mux7.IN3 +RA1[1] => Mux8.IN3 +RA1[1] => Mux9.IN3 +RA1[1] => Mux10.IN3 +RA1[1] => Mux11.IN3 +RA1[1] => Mux12.IN3 +RA1[1] => Mux13.IN3 +RA1[1] => Mux14.IN3 +RA1[1] => Mux15.IN3 +RA1[1] => Mux16.IN3 +RA1[1] => Mux17.IN3 +RA1[1] => Mux18.IN3 +RA1[1] => Mux19.IN3 +RA1[1] => Mux20.IN3 +RA1[1] => Mux21.IN3 +RA1[1] => Mux22.IN3 +RA1[1] => Mux23.IN3 +RA1[1] => Mux24.IN3 +RA1[1] => Mux25.IN3 +RA1[1] => Mux26.IN3 +RA1[1] => Mux27.IN3 +RA1[1] => Mux28.IN3 +RA1[1] => Mux29.IN3 +RA1[1] => Mux30.IN3 +RA1[1] => Mux31.IN3 +RA1[2] => Mux0.IN2 +RA1[2] => Mux1.IN2 +RA1[2] => Mux2.IN2 +RA1[2] => Mux3.IN2 +RA1[2] => Mux4.IN2 +RA1[2] => Mux5.IN2 +RA1[2] => Mux6.IN2 +RA1[2] => Mux7.IN2 +RA1[2] => Mux8.IN2 +RA1[2] => Mux9.IN2 +RA1[2] => Mux10.IN2 +RA1[2] => Mux11.IN2 +RA1[2] => Mux12.IN2 +RA1[2] => Mux13.IN2 +RA1[2] => Mux14.IN2 +RA1[2] => Mux15.IN2 +RA1[2] => Mux16.IN2 +RA1[2] => Mux17.IN2 +RA1[2] => Mux18.IN2 +RA1[2] => Mux19.IN2 +RA1[2] => Mux20.IN2 +RA1[2] => Mux21.IN2 +RA1[2] => Mux22.IN2 +RA1[2] => Mux23.IN2 +RA1[2] => Mux24.IN2 +RA1[2] => Mux25.IN2 +RA1[2] => Mux26.IN2 +RA1[2] => Mux27.IN2 +RA1[2] => Mux28.IN2 +RA1[2] => Mux29.IN2 +RA1[2] => Mux30.IN2 +RA1[2] => Mux31.IN2 +RA1[3] => Mux0.IN1 +RA1[3] => Mux1.IN1 +RA1[3] => Mux2.IN1 +RA1[3] => Mux3.IN1 +RA1[3] => Mux4.IN1 +RA1[3] => Mux5.IN1 +RA1[3] => Mux6.IN1 +RA1[3] => Mux7.IN1 +RA1[3] => Mux8.IN1 +RA1[3] => Mux9.IN1 +RA1[3] => Mux10.IN1 +RA1[3] => Mux11.IN1 +RA1[3] => Mux12.IN1 +RA1[3] => Mux13.IN1 +RA1[3] => Mux14.IN1 +RA1[3] => Mux15.IN1 +RA1[3] => Mux16.IN1 +RA1[3] => Mux17.IN1 +RA1[3] => Mux18.IN1 +RA1[3] => Mux19.IN1 +RA1[3] => Mux20.IN1 +RA1[3] => Mux21.IN1 +RA1[3] => Mux22.IN1 +RA1[3] => Mux23.IN1 +RA1[3] => Mux24.IN1 +RA1[3] => Mux25.IN1 +RA1[3] => Mux26.IN1 +RA1[3] => Mux27.IN1 +RA1[3] => Mux28.IN1 +RA1[3] => Mux29.IN1 +RA1[3] => Mux30.IN1 +RA1[3] => Mux31.IN1 +RA1[4] => Mux0.IN0 +RA1[4] => Mux1.IN0 +RA1[4] => Mux2.IN0 +RA1[4] => Mux3.IN0 +RA1[4] => Mux4.IN0 +RA1[4] => Mux5.IN0 +RA1[4] => Mux6.IN0 +RA1[4] => Mux7.IN0 +RA1[4] => Mux8.IN0 +RA1[4] => Mux9.IN0 +RA1[4] => Mux10.IN0 +RA1[4] => Mux11.IN0 +RA1[4] => Mux12.IN0 +RA1[4] => Mux13.IN0 +RA1[4] => Mux14.IN0 +RA1[4] => Mux15.IN0 +RA1[4] => Mux16.IN0 +RA1[4] => Mux17.IN0 +RA1[4] => Mux18.IN0 +RA1[4] => Mux19.IN0 +RA1[4] => Mux20.IN0 +RA1[4] => Mux21.IN0 +RA1[4] => Mux22.IN0 +RA1[4] => Mux23.IN0 +RA1[4] => Mux24.IN0 +RA1[4] => Mux25.IN0 +RA1[4] => Mux26.IN0 +RA1[4] => Mux27.IN0 +RA1[4] => Mux28.IN0 +RA1[4] => Mux29.IN0 +RA1[4] => Mux30.IN0 +RA1[4] => Mux31.IN0 +RD1[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE +RD1[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE +RD1[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE +RD1[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE +RD1[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE +RD1[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE +RD1[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE +RD1[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE +RD1[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE +RD1[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE +RD1[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE +RD1[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE +RD1[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE +RD1[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE +RD1[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE +RD1[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE +RD1[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE +RD1[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE +RD1[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE +RD1[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE +RD1[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE +RD1[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE +RD1[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE +RD1[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE +RD1[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE +RD1[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE +RD1[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +RD1[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +RD1[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +RD1[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +RD1[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +RD1[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +RA2[0] => Mux32.IN4 +RA2[0] => Mux33.IN4 +RA2[0] => Mux34.IN4 +RA2[0] => Mux35.IN4 +RA2[0] => Mux36.IN4 +RA2[0] => Mux37.IN4 +RA2[0] => Mux38.IN4 +RA2[0] => Mux39.IN4 +RA2[0] => Mux40.IN4 +RA2[0] => Mux41.IN4 +RA2[0] => Mux42.IN4 +RA2[0] => Mux43.IN4 +RA2[0] => Mux44.IN4 +RA2[0] => Mux45.IN4 +RA2[0] => Mux46.IN4 +RA2[0] => Mux47.IN4 +RA2[0] => Mux48.IN4 +RA2[0] => Mux49.IN4 +RA2[0] => Mux50.IN4 +RA2[0] => Mux51.IN4 +RA2[0] => Mux52.IN4 +RA2[0] => Mux53.IN4 +RA2[0] => Mux54.IN4 +RA2[0] => Mux55.IN4 +RA2[0] => Mux56.IN4 +RA2[0] => Mux57.IN4 +RA2[0] => Mux58.IN4 +RA2[0] => Mux59.IN4 +RA2[0] => Mux60.IN4 +RA2[0] => Mux61.IN4 +RA2[0] => Mux62.IN4 +RA2[0] => Mux63.IN4 +RA2[1] => Mux32.IN3 +RA2[1] => Mux33.IN3 +RA2[1] => Mux34.IN3 +RA2[1] => Mux35.IN3 +RA2[1] => Mux36.IN3 +RA2[1] => Mux37.IN3 +RA2[1] => Mux38.IN3 +RA2[1] => Mux39.IN3 +RA2[1] => Mux40.IN3 +RA2[1] => Mux41.IN3 +RA2[1] => Mux42.IN3 +RA2[1] => Mux43.IN3 +RA2[1] => Mux44.IN3 +RA2[1] => Mux45.IN3 +RA2[1] => Mux46.IN3 +RA2[1] => Mux47.IN3 +RA2[1] => Mux48.IN3 +RA2[1] => Mux49.IN3 +RA2[1] => Mux50.IN3 +RA2[1] => Mux51.IN3 +RA2[1] => Mux52.IN3 +RA2[1] => Mux53.IN3 +RA2[1] => Mux54.IN3 +RA2[1] => Mux55.IN3 +RA2[1] => Mux56.IN3 +RA2[1] => Mux57.IN3 +RA2[1] => Mux58.IN3 +RA2[1] => Mux59.IN3 +RA2[1] => Mux60.IN3 +RA2[1] => Mux61.IN3 +RA2[1] => Mux62.IN3 +RA2[1] => Mux63.IN3 +RA2[2] => Mux32.IN2 +RA2[2] => Mux33.IN2 +RA2[2] => Mux34.IN2 +RA2[2] => Mux35.IN2 +RA2[2] => Mux36.IN2 +RA2[2] => Mux37.IN2 +RA2[2] => Mux38.IN2 +RA2[2] => Mux39.IN2 +RA2[2] => Mux40.IN2 +RA2[2] => Mux41.IN2 +RA2[2] => Mux42.IN2 +RA2[2] => Mux43.IN2 +RA2[2] => Mux44.IN2 +RA2[2] => Mux45.IN2 +RA2[2] => Mux46.IN2 +RA2[2] => Mux47.IN2 +RA2[2] => Mux48.IN2 +RA2[2] => Mux49.IN2 +RA2[2] => Mux50.IN2 +RA2[2] => Mux51.IN2 +RA2[2] => Mux52.IN2 +RA2[2] => Mux53.IN2 +RA2[2] => Mux54.IN2 +RA2[2] => Mux55.IN2 +RA2[2] => Mux56.IN2 +RA2[2] => Mux57.IN2 +RA2[2] => Mux58.IN2 +RA2[2] => Mux59.IN2 +RA2[2] => Mux60.IN2 +RA2[2] => Mux61.IN2 +RA2[2] => Mux62.IN2 +RA2[2] => Mux63.IN2 +RA2[3] => Mux32.IN1 +RA2[3] => Mux33.IN1 +RA2[3] => Mux34.IN1 +RA2[3] => Mux35.IN1 +RA2[3] => Mux36.IN1 +RA2[3] => Mux37.IN1 +RA2[3] => Mux38.IN1 +RA2[3] => Mux39.IN1 +RA2[3] => Mux40.IN1 +RA2[3] => Mux41.IN1 +RA2[3] => Mux42.IN1 +RA2[3] => Mux43.IN1 +RA2[3] => Mux44.IN1 +RA2[3] => Mux45.IN1 +RA2[3] => Mux46.IN1 +RA2[3] => Mux47.IN1 +RA2[3] => Mux48.IN1 +RA2[3] => Mux49.IN1 +RA2[3] => Mux50.IN1 +RA2[3] => Mux51.IN1 +RA2[3] => Mux52.IN1 +RA2[3] => Mux53.IN1 +RA2[3] => Mux54.IN1 +RA2[3] => Mux55.IN1 +RA2[3] => Mux56.IN1 +RA2[3] => Mux57.IN1 +RA2[3] => Mux58.IN1 +RA2[3] => Mux59.IN1 +RA2[3] => Mux60.IN1 +RA2[3] => Mux61.IN1 +RA2[3] => Mux62.IN1 +RA2[3] => Mux63.IN1 +RA2[4] => Mux32.IN0 +RA2[4] => Mux33.IN0 +RA2[4] => Mux34.IN0 +RA2[4] => Mux35.IN0 +RA2[4] => Mux36.IN0 +RA2[4] => Mux37.IN0 +RA2[4] => Mux38.IN0 +RA2[4] => Mux39.IN0 +RA2[4] => Mux40.IN0 +RA2[4] => Mux41.IN0 +RA2[4] => Mux42.IN0 +RA2[4] => Mux43.IN0 +RA2[4] => Mux44.IN0 +RA2[4] => Mux45.IN0 +RA2[4] => Mux46.IN0 +RA2[4] => Mux47.IN0 +RA2[4] => Mux48.IN0 +RA2[4] => Mux49.IN0 +RA2[4] => Mux50.IN0 +RA2[4] => Mux51.IN0 +RA2[4] => Mux52.IN0 +RA2[4] => Mux53.IN0 +RA2[4] => Mux54.IN0 +RA2[4] => Mux55.IN0 +RA2[4] => Mux56.IN0 +RA2[4] => Mux57.IN0 +RA2[4] => Mux58.IN0 +RA2[4] => Mux59.IN0 +RA2[4] => Mux60.IN0 +RA2[4] => Mux61.IN0 +RA2[4] => Mux62.IN0 +RA2[4] => Mux63.IN0 +RD2[0] <= Mux63.DB_MAX_OUTPUT_PORT_TYPE +RD2[1] <= Mux62.DB_MAX_OUTPUT_PORT_TYPE +RD2[2] <= Mux61.DB_MAX_OUTPUT_PORT_TYPE +RD2[3] <= Mux60.DB_MAX_OUTPUT_PORT_TYPE +RD2[4] <= Mux59.DB_MAX_OUTPUT_PORT_TYPE +RD2[5] <= Mux58.DB_MAX_OUTPUT_PORT_TYPE +RD2[6] <= Mux57.DB_MAX_OUTPUT_PORT_TYPE +RD2[7] <= Mux56.DB_MAX_OUTPUT_PORT_TYPE +RD2[8] <= Mux55.DB_MAX_OUTPUT_PORT_TYPE +RD2[9] <= Mux54.DB_MAX_OUTPUT_PORT_TYPE +RD2[10] <= Mux53.DB_MAX_OUTPUT_PORT_TYPE +RD2[11] <= Mux52.DB_MAX_OUTPUT_PORT_TYPE +RD2[12] <= Mux51.DB_MAX_OUTPUT_PORT_TYPE +RD2[13] <= Mux50.DB_MAX_OUTPUT_PORT_TYPE +RD2[14] <= Mux49.DB_MAX_OUTPUT_PORT_TYPE +RD2[15] <= Mux48.DB_MAX_OUTPUT_PORT_TYPE +RD2[16] <= Mux47.DB_MAX_OUTPUT_PORT_TYPE +RD2[17] <= Mux46.DB_MAX_OUTPUT_PORT_TYPE +RD2[18] <= Mux45.DB_MAX_OUTPUT_PORT_TYPE +RD2[19] <= Mux44.DB_MAX_OUTPUT_PORT_TYPE +RD2[20] <= Mux43.DB_MAX_OUTPUT_PORT_TYPE +RD2[21] <= Mux42.DB_MAX_OUTPUT_PORT_TYPE +RD2[22] <= Mux41.DB_MAX_OUTPUT_PORT_TYPE +RD2[23] <= Mux40.DB_MAX_OUTPUT_PORT_TYPE +RD2[24] <= Mux39.DB_MAX_OUTPUT_PORT_TYPE +RD2[25] <= Mux38.DB_MAX_OUTPUT_PORT_TYPE +RD2[26] <= Mux37.DB_MAX_OUTPUT_PORT_TYPE +RD2[27] <= Mux36.DB_MAX_OUTPUT_PORT_TYPE +RD2[28] <= Mux35.DB_MAX_OUTPUT_PORT_TYPE +RD2[29] <= Mux34.DB_MAX_OUTPUT_PORT_TYPE +RD2[30] <= Mux33.DB_MAX_OUTPUT_PORT_TYPE +RD2[31] <= Mux32.DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][0] <= regs[31][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][1] <= regs[31][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][2] <= regs[31][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][3] <= regs[31][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][4] <= regs[31][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][5] <= regs[31][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][6] <= regs[31][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][7] <= regs[31][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][8] <= regs[31][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][9] <= regs[31][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][10] <= regs[31][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][11] <= regs[31][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][12] <= regs[31][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][13] <= regs[31][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][14] <= regs[31][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][15] <= regs[31][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][16] <= regs[31][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][17] <= regs[31][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][18] <= regs[31][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][19] <= regs[31][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][20] <= regs[31][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][21] <= regs[31][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][22] <= regs[31][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][23] <= regs[31][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][24] <= regs[31][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][25] <= regs[31][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][26] <= regs[31][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][27] <= regs[31][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][28] <= regs[31][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][29] <= regs[31][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][30] <= regs[31][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[31][31] <= regs[31][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][0] <= regs[30][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][1] <= regs[30][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][2] <= regs[30][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][3] <= regs[30][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][4] <= regs[30][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][5] <= regs[30][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][6] <= regs[30][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][7] <= regs[30][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][8] <= regs[30][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][9] <= regs[30][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][10] <= regs[30][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][11] <= regs[30][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][12] <= regs[30][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][13] <= regs[30][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][14] <= regs[30][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][15] <= regs[30][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][16] <= regs[30][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][17] <= regs[30][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][18] <= regs[30][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][19] <= regs[30][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][20] <= regs[30][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][21] <= regs[30][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][22] <= regs[30][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][23] <= regs[30][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][24] <= regs[30][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][25] <= regs[30][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][26] <= regs[30][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][27] <= regs[30][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][28] <= regs[30][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][29] <= regs[30][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][30] <= regs[30][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[30][31] <= regs[30][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][0] <= regs[29][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][1] <= regs[29][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][2] <= regs[29][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][3] <= regs[29][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][4] <= regs[29][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][5] <= regs[29][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][6] <= regs[29][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][7] <= regs[29][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][8] <= regs[29][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][9] <= regs[29][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][10] <= regs[29][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][11] <= regs[29][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][12] <= regs[29][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][13] <= regs[29][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][14] <= regs[29][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][15] <= regs[29][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][16] <= regs[29][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][17] <= regs[29][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][18] <= regs[29][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][19] <= regs[29][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][20] <= regs[29][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][21] <= regs[29][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][22] <= regs[29][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][23] <= regs[29][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][24] <= regs[29][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][25] <= regs[29][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][26] <= regs[29][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][27] <= regs[29][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][28] <= regs[29][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][29] <= regs[29][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][30] <= regs[29][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[29][31] <= regs[29][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][0] <= regs[28][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][1] <= regs[28][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][2] <= regs[28][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][3] <= regs[28][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][4] <= regs[28][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][5] <= regs[28][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][6] <= regs[28][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][7] <= regs[28][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][8] <= regs[28][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][9] <= regs[28][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][10] <= regs[28][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][11] <= regs[28][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][12] <= regs[28][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][13] <= regs[28][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][14] <= regs[28][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][15] <= regs[28][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][16] <= regs[28][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][17] <= regs[28][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][18] <= regs[28][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][19] <= regs[28][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][20] <= regs[28][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][21] <= regs[28][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][22] <= regs[28][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][23] <= regs[28][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][24] <= regs[28][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][25] <= regs[28][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][26] <= regs[28][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][27] <= regs[28][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][28] <= regs[28][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][29] <= regs[28][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][30] <= regs[28][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[28][31] <= regs[28][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][0] <= regs[27][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][1] <= regs[27][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][2] <= regs[27][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][3] <= regs[27][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][4] <= regs[27][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][5] <= regs[27][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][6] <= regs[27][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][7] <= regs[27][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][8] <= regs[27][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][9] <= regs[27][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][10] <= regs[27][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][11] <= regs[27][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][12] <= regs[27][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][13] <= regs[27][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][14] <= regs[27][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][15] <= regs[27][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][16] <= regs[27][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][17] <= regs[27][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][18] <= regs[27][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][19] <= regs[27][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][20] <= regs[27][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][21] <= regs[27][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][22] <= regs[27][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][23] <= regs[27][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][24] <= regs[27][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][25] <= regs[27][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][26] <= regs[27][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][27] <= regs[27][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][28] <= regs[27][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][29] <= regs[27][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][30] <= regs[27][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[27][31] <= regs[27][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][0] <= regs[26][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][1] <= regs[26][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][2] <= regs[26][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][3] <= regs[26][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][4] <= regs[26][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][5] <= regs[26][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][6] <= regs[26][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][7] <= regs[26][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][8] <= regs[26][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][9] <= regs[26][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][10] <= regs[26][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][11] <= regs[26][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][12] <= regs[26][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][13] <= regs[26][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][14] <= regs[26][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][15] <= regs[26][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][16] <= regs[26][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][17] <= regs[26][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][18] <= regs[26][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][19] <= regs[26][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][20] <= regs[26][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][21] <= regs[26][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][22] <= regs[26][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][23] <= regs[26][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][24] <= regs[26][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][25] <= regs[26][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][26] <= regs[26][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][27] <= regs[26][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][28] <= regs[26][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][29] <= regs[26][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][30] <= regs[26][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[26][31] <= regs[26][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][0] <= regs[25][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][1] <= regs[25][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][2] <= regs[25][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][3] <= regs[25][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][4] <= regs[25][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][5] <= regs[25][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][6] <= regs[25][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][7] <= regs[25][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][8] <= regs[25][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][9] <= regs[25][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][10] <= regs[25][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][11] <= regs[25][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][12] <= regs[25][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][13] <= regs[25][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][14] <= regs[25][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][15] <= regs[25][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][16] <= regs[25][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][17] <= regs[25][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][18] <= regs[25][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][19] <= regs[25][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][20] <= regs[25][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][21] <= regs[25][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][22] <= regs[25][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][23] <= regs[25][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][24] <= regs[25][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][25] <= regs[25][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][26] <= regs[25][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][27] <= regs[25][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][28] <= regs[25][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][29] <= regs[25][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][30] <= regs[25][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[25][31] <= regs[25][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][0] <= regs[24][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][1] <= regs[24][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][2] <= regs[24][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][3] <= regs[24][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][4] <= regs[24][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][5] <= regs[24][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][6] <= regs[24][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][7] <= regs[24][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][8] <= regs[24][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][9] <= regs[24][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][10] <= regs[24][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][11] <= regs[24][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][12] <= regs[24][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][13] <= regs[24][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][14] <= regs[24][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][15] <= regs[24][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][16] <= regs[24][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][17] <= regs[24][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][18] <= regs[24][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][19] <= regs[24][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][20] <= regs[24][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][21] <= regs[24][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][22] <= regs[24][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][23] <= regs[24][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][24] <= regs[24][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][25] <= regs[24][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][26] <= regs[24][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][27] <= regs[24][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][28] <= regs[24][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][29] <= regs[24][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][30] <= regs[24][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[24][31] <= regs[24][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][0] <= regs[23][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][1] <= regs[23][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][2] <= regs[23][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][3] <= regs[23][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][4] <= regs[23][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][5] <= regs[23][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][6] <= regs[23][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][7] <= regs[23][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][8] <= regs[23][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][9] <= regs[23][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][10] <= regs[23][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][11] <= regs[23][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][12] <= regs[23][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][13] <= regs[23][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][14] <= regs[23][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][15] <= regs[23][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][16] <= regs[23][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][17] <= regs[23][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][18] <= regs[23][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][19] <= regs[23][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][20] <= regs[23][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][21] <= regs[23][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][22] <= regs[23][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][23] <= regs[23][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][24] <= regs[23][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][25] <= regs[23][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][26] <= regs[23][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][27] <= regs[23][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][28] <= regs[23][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][29] <= regs[23][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][30] <= regs[23][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[23][31] <= regs[23][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][0] <= regs[22][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][1] <= regs[22][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][2] <= regs[22][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][3] <= regs[22][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][4] <= regs[22][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][5] <= regs[22][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][6] <= regs[22][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][7] <= regs[22][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][8] <= regs[22][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][9] <= regs[22][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][10] <= regs[22][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][11] <= regs[22][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][12] <= regs[22][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][13] <= regs[22][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][14] <= regs[22][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][15] <= regs[22][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][16] <= regs[22][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][17] <= regs[22][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][18] <= regs[22][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][19] <= regs[22][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][20] <= regs[22][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][21] <= regs[22][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][22] <= regs[22][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][23] <= regs[22][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][24] <= regs[22][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][25] <= regs[22][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][26] <= regs[22][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][27] <= regs[22][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][28] <= regs[22][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][29] <= regs[22][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][30] <= regs[22][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[22][31] <= regs[22][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][0] <= regs[21][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][1] <= regs[21][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][2] <= regs[21][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][3] <= regs[21][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][4] <= regs[21][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][5] <= regs[21][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][6] <= regs[21][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][7] <= regs[21][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][8] <= regs[21][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][9] <= regs[21][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][10] <= regs[21][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][11] <= regs[21][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][12] <= regs[21][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][13] <= regs[21][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][14] <= regs[21][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][15] <= regs[21][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][16] <= regs[21][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][17] <= regs[21][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][18] <= regs[21][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][19] <= regs[21][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][20] <= regs[21][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][21] <= regs[21][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][22] <= regs[21][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][23] <= regs[21][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][24] <= regs[21][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][25] <= regs[21][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][26] <= regs[21][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][27] <= regs[21][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][28] <= regs[21][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][29] <= regs[21][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][30] <= regs[21][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[21][31] <= regs[21][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][0] <= regs[20][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][1] <= regs[20][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][2] <= regs[20][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][3] <= regs[20][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][4] <= regs[20][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][5] <= regs[20][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][6] <= regs[20][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][7] <= regs[20][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][8] <= regs[20][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][9] <= regs[20][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][10] <= regs[20][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][11] <= regs[20][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][12] <= regs[20][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][13] <= regs[20][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][14] <= regs[20][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][15] <= regs[20][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][16] <= regs[20][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][17] <= regs[20][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][18] <= regs[20][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][19] <= regs[20][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][20] <= regs[20][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][21] <= regs[20][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][22] <= regs[20][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][23] <= regs[20][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][24] <= regs[20][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][25] <= regs[20][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][26] <= regs[20][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][27] <= regs[20][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][28] <= regs[20][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][29] <= regs[20][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][30] <= regs[20][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[20][31] <= regs[20][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][0] <= regs[19][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][1] <= regs[19][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][2] <= regs[19][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][3] <= regs[19][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][4] <= regs[19][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][5] <= regs[19][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][6] <= regs[19][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][7] <= regs[19][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][8] <= regs[19][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][9] <= regs[19][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][10] <= regs[19][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][11] <= regs[19][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][12] <= regs[19][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][13] <= regs[19][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][14] <= regs[19][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][15] <= regs[19][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][16] <= regs[19][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][17] <= regs[19][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][18] <= regs[19][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][19] <= regs[19][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][20] <= regs[19][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][21] <= regs[19][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][22] <= regs[19][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][23] <= regs[19][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][24] <= regs[19][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][25] <= regs[19][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][26] <= regs[19][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][27] <= regs[19][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][28] <= regs[19][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][29] <= regs[19][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][30] <= regs[19][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[19][31] <= regs[19][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][0] <= regs[18][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][1] <= regs[18][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][2] <= regs[18][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][3] <= regs[18][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][4] <= regs[18][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][5] <= regs[18][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][6] <= regs[18][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][7] <= regs[18][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][8] <= regs[18][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][9] <= regs[18][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][10] <= regs[18][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][11] <= regs[18][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][12] <= regs[18][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][13] <= regs[18][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][14] <= regs[18][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][15] <= regs[18][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][16] <= regs[18][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][17] <= regs[18][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][18] <= regs[18][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][19] <= regs[18][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][20] <= regs[18][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][21] <= regs[18][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][22] <= regs[18][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][23] <= regs[18][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][24] <= regs[18][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][25] <= regs[18][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][26] <= regs[18][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][27] <= regs[18][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][28] <= regs[18][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][29] <= regs[18][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][30] <= regs[18][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[18][31] <= regs[18][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][0] <= regs[17][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][1] <= regs[17][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][2] <= regs[17][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][3] <= regs[17][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][4] <= regs[17][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][5] <= regs[17][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][6] <= regs[17][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][7] <= regs[17][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][8] <= regs[17][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][9] <= regs[17][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][10] <= regs[17][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][11] <= regs[17][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][12] <= regs[17][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][13] <= regs[17][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][14] <= regs[17][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][15] <= regs[17][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][16] <= regs[17][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][17] <= regs[17][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][18] <= regs[17][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][19] <= regs[17][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][20] <= regs[17][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][21] <= regs[17][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][22] <= regs[17][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][23] <= regs[17][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][24] <= regs[17][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][25] <= regs[17][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][26] <= regs[17][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][27] <= regs[17][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][28] <= regs[17][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][29] <= regs[17][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][30] <= regs[17][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[17][31] <= regs[17][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][0] <= regs[16][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][1] <= regs[16][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][2] <= regs[16][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][3] <= regs[16][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][4] <= regs[16][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][5] <= regs[16][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][6] <= regs[16][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][7] <= regs[16][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][8] <= regs[16][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][9] <= regs[16][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][10] <= regs[16][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][11] <= regs[16][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][12] <= regs[16][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][13] <= regs[16][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][14] <= regs[16][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][15] <= regs[16][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][16] <= regs[16][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][17] <= regs[16][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][18] <= regs[16][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][19] <= regs[16][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][20] <= regs[16][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][21] <= regs[16][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][22] <= regs[16][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][23] <= regs[16][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][24] <= regs[16][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][25] <= regs[16][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][26] <= regs[16][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][27] <= regs[16][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][28] <= regs[16][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][29] <= regs[16][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][30] <= regs[16][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[16][31] <= regs[16][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][0] <= regs[15][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][1] <= regs[15][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][2] <= regs[15][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][3] <= regs[15][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][4] <= regs[15][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][5] <= regs[15][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][6] <= regs[15][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][7] <= regs[15][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][8] <= regs[15][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][9] <= regs[15][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][10] <= regs[15][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][11] <= regs[15][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][12] <= regs[15][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][13] <= regs[15][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][14] <= regs[15][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][15] <= regs[15][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][16] <= regs[15][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][17] <= regs[15][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][18] <= regs[15][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][19] <= regs[15][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][20] <= regs[15][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][21] <= regs[15][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][22] <= regs[15][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][23] <= regs[15][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][24] <= regs[15][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][25] <= regs[15][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][26] <= regs[15][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][27] <= regs[15][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][28] <= regs[15][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][29] <= regs[15][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][30] <= regs[15][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[15][31] <= regs[15][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][0] <= regs[14][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][1] <= regs[14][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][2] <= regs[14][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][3] <= regs[14][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][4] <= regs[14][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][5] <= regs[14][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][6] <= regs[14][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][7] <= regs[14][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][8] <= regs[14][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][9] <= regs[14][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][10] <= regs[14][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][11] <= regs[14][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][12] <= regs[14][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][13] <= regs[14][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][14] <= regs[14][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][15] <= regs[14][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][16] <= regs[14][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][17] <= regs[14][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][18] <= regs[14][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][19] <= regs[14][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][20] <= regs[14][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][21] <= regs[14][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][22] <= regs[14][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][23] <= regs[14][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][24] <= regs[14][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][25] <= regs[14][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][26] <= regs[14][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][27] <= regs[14][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][28] <= regs[14][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][29] <= regs[14][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][30] <= regs[14][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[14][31] <= regs[14][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][0] <= regs[13][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][1] <= regs[13][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][2] <= regs[13][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][3] <= regs[13][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][4] <= regs[13][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][5] <= regs[13][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][6] <= regs[13][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][7] <= regs[13][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][8] <= regs[13][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][9] <= regs[13][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][10] <= regs[13][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][11] <= regs[13][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][12] <= regs[13][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][13] <= regs[13][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][14] <= regs[13][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][15] <= regs[13][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][16] <= regs[13][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][17] <= regs[13][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][18] <= regs[13][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][19] <= regs[13][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][20] <= regs[13][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][21] <= regs[13][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][22] <= regs[13][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][23] <= regs[13][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][24] <= regs[13][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][25] <= regs[13][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][26] <= regs[13][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][27] <= regs[13][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][28] <= regs[13][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][29] <= regs[13][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][30] <= regs[13][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[13][31] <= regs[13][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][0] <= regs[12][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][1] <= regs[12][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][2] <= regs[12][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][3] <= regs[12][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][4] <= regs[12][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][5] <= regs[12][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][6] <= regs[12][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][7] <= regs[12][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][8] <= regs[12][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][9] <= regs[12][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][10] <= regs[12][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][11] <= regs[12][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][12] <= regs[12][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][13] <= regs[12][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][14] <= regs[12][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][15] <= regs[12][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][16] <= regs[12][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][17] <= regs[12][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][18] <= regs[12][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][19] <= regs[12][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][20] <= regs[12][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][21] <= regs[12][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][22] <= regs[12][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][23] <= regs[12][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][24] <= regs[12][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][25] <= regs[12][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][26] <= regs[12][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][27] <= regs[12][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][28] <= regs[12][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][29] <= regs[12][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][30] <= regs[12][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[12][31] <= regs[12][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][0] <= regs[11][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][1] <= regs[11][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][2] <= regs[11][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][3] <= regs[11][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][4] <= regs[11][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][5] <= regs[11][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][6] <= regs[11][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][7] <= regs[11][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][8] <= regs[11][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][9] <= regs[11][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][10] <= regs[11][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][11] <= regs[11][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][12] <= regs[11][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][13] <= regs[11][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][14] <= regs[11][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][15] <= regs[11][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][16] <= regs[11][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][17] <= regs[11][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][18] <= regs[11][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][19] <= regs[11][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][20] <= regs[11][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][21] <= regs[11][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][22] <= regs[11][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][23] <= regs[11][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][24] <= regs[11][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][25] <= regs[11][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][26] <= regs[11][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][27] <= regs[11][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][28] <= regs[11][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][29] <= regs[11][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][30] <= regs[11][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[11][31] <= regs[11][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][0] <= regs[10][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][1] <= regs[10][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][2] <= regs[10][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][3] <= regs[10][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][4] <= regs[10][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][5] <= regs[10][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][6] <= regs[10][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][7] <= regs[10][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][8] <= regs[10][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][9] <= regs[10][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][10] <= regs[10][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][11] <= regs[10][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][12] <= regs[10][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][13] <= regs[10][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][14] <= regs[10][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][15] <= regs[10][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][16] <= regs[10][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][17] <= regs[10][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][18] <= regs[10][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][19] <= regs[10][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][20] <= regs[10][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][21] <= regs[10][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][22] <= regs[10][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][23] <= regs[10][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][24] <= regs[10][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][25] <= regs[10][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][26] <= regs[10][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][27] <= regs[10][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][28] <= regs[10][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][29] <= regs[10][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][30] <= regs[10][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[10][31] <= regs[10][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][0] <= regs[9][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][1] <= regs[9][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][2] <= regs[9][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][3] <= regs[9][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][4] <= regs[9][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][5] <= regs[9][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][6] <= regs[9][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][7] <= regs[9][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][8] <= regs[9][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][9] <= regs[9][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][10] <= regs[9][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][11] <= regs[9][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][12] <= regs[9][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][13] <= regs[9][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][14] <= regs[9][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][15] <= regs[9][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][16] <= regs[9][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][17] <= regs[9][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][18] <= regs[9][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][19] <= regs[9][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][20] <= regs[9][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][21] <= regs[9][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][22] <= regs[9][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][23] <= regs[9][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][24] <= regs[9][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][25] <= regs[9][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][26] <= regs[9][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][27] <= regs[9][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][28] <= regs[9][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][29] <= regs[9][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][30] <= regs[9][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[9][31] <= regs[9][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][0] <= regs[8][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][1] <= regs[8][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][2] <= regs[8][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][3] <= regs[8][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][4] <= regs[8][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][5] <= regs[8][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][6] <= regs[8][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][7] <= regs[8][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][8] <= regs[8][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][9] <= regs[8][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][10] <= regs[8][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][11] <= regs[8][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][12] <= regs[8][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][13] <= regs[8][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][14] <= regs[8][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][15] <= regs[8][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][16] <= regs[8][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][17] <= regs[8][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][18] <= regs[8][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][19] <= regs[8][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][20] <= regs[8][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][21] <= regs[8][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][22] <= regs[8][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][23] <= regs[8][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][24] <= regs[8][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][25] <= regs[8][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][26] <= regs[8][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][27] <= regs[8][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][28] <= regs[8][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][29] <= regs[8][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][30] <= regs[8][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[8][31] <= regs[8][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][0] <= regs[7][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][1] <= regs[7][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][2] <= regs[7][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][3] <= regs[7][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][4] <= regs[7][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][5] <= regs[7][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][6] <= regs[7][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][7] <= regs[7][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][8] <= regs[7][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][9] <= regs[7][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][10] <= regs[7][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][11] <= regs[7][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][12] <= regs[7][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][13] <= regs[7][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][14] <= regs[7][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][15] <= regs[7][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][16] <= regs[7][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][17] <= regs[7][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][18] <= regs[7][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][19] <= regs[7][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][20] <= regs[7][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][21] <= regs[7][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][22] <= regs[7][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][23] <= regs[7][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][24] <= regs[7][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][25] <= regs[7][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][26] <= regs[7][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][27] <= regs[7][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][28] <= regs[7][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][29] <= regs[7][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][30] <= regs[7][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[7][31] <= regs[7][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][0] <= regs[6][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][1] <= regs[6][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][2] <= regs[6][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][3] <= regs[6][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][4] <= regs[6][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][5] <= regs[6][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][6] <= regs[6][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][7] <= regs[6][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][8] <= regs[6][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][9] <= regs[6][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][10] <= regs[6][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][11] <= regs[6][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][12] <= regs[6][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][13] <= regs[6][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][14] <= regs[6][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][15] <= regs[6][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][16] <= regs[6][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][17] <= regs[6][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][18] <= regs[6][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][19] <= regs[6][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][20] <= regs[6][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][21] <= regs[6][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][22] <= regs[6][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][23] <= regs[6][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][24] <= regs[6][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][25] <= regs[6][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][26] <= regs[6][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][27] <= regs[6][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][28] <= regs[6][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][29] <= regs[6][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][30] <= regs[6][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[6][31] <= regs[6][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][0] <= regs[5][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][1] <= regs[5][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][2] <= regs[5][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][3] <= regs[5][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][4] <= regs[5][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][5] <= regs[5][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][6] <= regs[5][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][7] <= regs[5][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][8] <= regs[5][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][9] <= regs[5][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][10] <= regs[5][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][11] <= regs[5][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][12] <= regs[5][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][13] <= regs[5][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][14] <= regs[5][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][15] <= regs[5][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][16] <= regs[5][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][17] <= regs[5][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][18] <= regs[5][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][19] <= regs[5][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][20] <= regs[5][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][21] <= regs[5][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][22] <= regs[5][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][23] <= regs[5][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][24] <= regs[5][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][25] <= regs[5][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][26] <= regs[5][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][27] <= regs[5][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][28] <= regs[5][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][29] <= regs[5][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][30] <= regs[5][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[5][31] <= regs[5][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][0] <= regs[4][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][1] <= regs[4][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][2] <= regs[4][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][3] <= regs[4][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][4] <= regs[4][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][5] <= regs[4][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][6] <= regs[4][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][7] <= regs[4][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][8] <= regs[4][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][9] <= regs[4][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][10] <= regs[4][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][11] <= regs[4][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][12] <= regs[4][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][13] <= regs[4][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][14] <= regs[4][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][15] <= regs[4][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][16] <= regs[4][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][17] <= regs[4][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][18] <= regs[4][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][19] <= regs[4][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][20] <= regs[4][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][21] <= regs[4][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][22] <= regs[4][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][23] <= regs[4][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][24] <= regs[4][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][25] <= regs[4][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][26] <= regs[4][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][27] <= regs[4][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][28] <= regs[4][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][29] <= regs[4][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][30] <= regs[4][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[4][31] <= regs[4][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][0] <= regs[3][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][1] <= regs[3][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][2] <= regs[3][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][3] <= regs[3][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][4] <= regs[3][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][5] <= regs[3][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][6] <= regs[3][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][7] <= regs[3][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][8] <= regs[3][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][9] <= regs[3][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][10] <= regs[3][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][11] <= regs[3][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][12] <= regs[3][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][13] <= regs[3][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][14] <= regs[3][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][15] <= regs[3][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][16] <= regs[3][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][17] <= regs[3][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][18] <= regs[3][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][19] <= regs[3][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][20] <= regs[3][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][21] <= regs[3][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][22] <= regs[3][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][23] <= regs[3][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][24] <= regs[3][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][25] <= regs[3][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][26] <= regs[3][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][27] <= regs[3][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][28] <= regs[3][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][29] <= regs[3][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][30] <= regs[3][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[3][31] <= regs[3][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][0] <= regs[2][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][1] <= regs[2][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][2] <= regs[2][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][3] <= regs[2][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][4] <= regs[2][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][5] <= regs[2][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][6] <= regs[2][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][7] <= regs[2][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][8] <= regs[2][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][9] <= regs[2][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][10] <= regs[2][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][11] <= regs[2][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][12] <= regs[2][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][13] <= regs[2][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][14] <= regs[2][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][15] <= regs[2][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][16] <= regs[2][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][17] <= regs[2][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][18] <= regs[2][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][19] <= regs[2][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][20] <= regs[2][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][21] <= regs[2][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][22] <= regs[2][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][23] <= regs[2][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][24] <= regs[2][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][25] <= regs[2][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][26] <= regs[2][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][27] <= regs[2][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][28] <= regs[2][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][29] <= regs[2][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][30] <= regs[2][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[2][31] <= regs[2][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][0] <= regs[1][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][1] <= regs[1][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][2] <= regs[1][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][3] <= regs[1][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][4] <= regs[1][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][5] <= regs[1][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][6] <= regs[1][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][7] <= regs[1][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][8] <= regs[1][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][9] <= regs[1][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][10] <= regs[1][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][11] <= regs[1][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][12] <= regs[1][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][13] <= regs[1][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][14] <= regs[1][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][15] <= regs[1][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][16] <= regs[1][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][17] <= regs[1][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][18] <= regs[1][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][19] <= regs[1][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][20] <= regs[1][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][21] <= regs[1][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][22] <= regs[1][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][23] <= regs[1][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][24] <= regs[1][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][25] <= regs[1][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][26] <= regs[1][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][27] <= regs[1][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][28] <= regs[1][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][29] <= regs[1][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][30] <= regs[1][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[1][31] <= regs[1][31].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][0] <= regs[0][0].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][1] <= regs[0][1].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][2] <= regs[0][2].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][3] <= regs[0][3].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][4] <= regs[0][4].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][5] <= regs[0][5].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][6] <= regs[0][6].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][7] <= regs[0][7].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][8] <= regs[0][8].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][9] <= regs[0][9].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][10] <= regs[0][10].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][11] <= regs[0][11].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][12] <= regs[0][12].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][13] <= regs[0][13].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][14] <= regs[0][14].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][15] <= regs[0][15].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][16] <= regs[0][16].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][17] <= regs[0][17].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][18] <= regs[0][18].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][19] <= regs[0][19].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][20] <= regs[0][20].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][21] <= regs[0][21].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][22] <= regs[0][22].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][23] <= regs[0][23].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][24] <= regs[0][24].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][25] <= regs[0][25].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][26] <= regs[0][26].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][27] <= regs[0][27].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][28] <= regs[0][28].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][29] <= regs[0][29].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][30] <= regs[0][30].DB_MAX_OUTPUT_PORT_TYPE +regs_out[0][31] <= regs[0][31].DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|sign_extender:SIGNEXT +op[0] => ext_val.OUTPUTSELECT +op[0] => ext_val.OUTPUTSELECT +val[0] => ext_val[0].DATAIN +val[1] => ext_val[1].DATAIN +val[2] => ext_val[2].DATAIN +val[3] => ext_val[3].DATAIN +val[4] => ext_val[4].DATAIN +val[5] => ext_val[5].DATAIN +val[6] => ext_val[6].DATAIN +val[7] => ext_val[7].DATAIN +val[8] => ext_val[8].DATAIN +val[9] => ext_val[9].DATAIN +val[10] => ext_val[10].DATAIN +val[11] => ext_val[11].DATAIN +val[12] => ext_val[12].DATAIN +val[13] => ext_val[13].DATAIN +val[14] => ext_val[14].DATAIN +val[15] => ext_val.DATAB +val[15] => ext_val.DATAB +val[15] => ext_val[15].DATAIN +ext_val[0] <= val[0].DB_MAX_OUTPUT_PORT_TYPE +ext_val[1] <= val[1].DB_MAX_OUTPUT_PORT_TYPE +ext_val[2] <= val[2].DB_MAX_OUTPUT_PORT_TYPE +ext_val[3] <= val[3].DB_MAX_OUTPUT_PORT_TYPE +ext_val[4] <= val[4].DB_MAX_OUTPUT_PORT_TYPE +ext_val[5] <= val[5].DB_MAX_OUTPUT_PORT_TYPE +ext_val[6] <= val[6].DB_MAX_OUTPUT_PORT_TYPE +ext_val[7] <= val[7].DB_MAX_OUTPUT_PORT_TYPE +ext_val[8] <= val[8].DB_MAX_OUTPUT_PORT_TYPE +ext_val[9] <= val[9].DB_MAX_OUTPUT_PORT_TYPE +ext_val[10] <= val[10].DB_MAX_OUTPUT_PORT_TYPE +ext_val[11] <= val[11].DB_MAX_OUTPUT_PORT_TYPE +ext_val[12] <= val[12].DB_MAX_OUTPUT_PORT_TYPE +ext_val[13] <= val[13].DB_MAX_OUTPUT_PORT_TYPE +ext_val[14] <= val[14].DB_MAX_OUTPUT_PORT_TYPE +ext_val[15] <= val[15].DB_MAX_OUTPUT_PORT_TYPE +ext_val[16] <= ext_val.DB_MAX_OUTPUT_PORT_TYPE +ext_val[17] <= ext_val.DB_MAX_OUTPUT_PORT_TYPE +ext_val[18] <= +ext_val[19] <= +ext_val[20] <= +ext_val[21] <= +ext_val[22] <= +ext_val[23] <= +ext_val[24] <= +ext_val[25] <= +ext_val[26] <= +ext_val[27] <= +ext_val[28] <= +ext_val[29] <= +ext_val[30] <= +ext_val[31] <= |assignment2|alu:ALU @@ -631,6 +4759,7 @@ OUT_1[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE OUT_1[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE flags[0] <= asu:adder_unit.port4 flags[1] <= asu:adder_unit.port5 +flags[2] <= Equal0.DB_MAX_OUTPUT_PORT_TYPE |assignment2|alu:ALU|asu:adder_unit @@ -1091,506 +5220,6 @@ Y[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE Y[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE -|assignment2|shifter:SHIFTER -op[0] => Mux0.IN8 -op[0] => Mux1.IN8 -op[0] => Mux2.IN8 -op[0] => Mux3.IN8 -op[0] => Mux4.IN8 -op[0] => Mux5.IN8 -op[0] => Mux6.IN8 -op[0] => Mux7.IN8 -op[0] => Mux8.IN8 -op[0] => Mux9.IN8 -op[0] => Mux10.IN8 -op[0] => Mux11.IN8 -op[0] => Mux12.IN8 -op[0] => Mux13.IN8 -op[0] => Mux14.IN8 -op[0] => Mux15.IN8 -op[0] => Mux16.IN8 -op[0] => Mux17.IN8 -op[0] => Mux18.IN8 -op[0] => Mux19.IN8 -op[0] => Mux20.IN8 -op[0] => Mux21.IN8 -op[0] => Mux22.IN8 -op[0] => Mux23.IN8 -op[0] => Mux24.IN8 -op[0] => Mux25.IN8 -op[0] => Mux26.IN8 -op[0] => Mux27.IN8 -op[0] => Mux28.IN8 -op[0] => Mux29.IN8 -op[0] => Mux30.IN8 -op[0] => Mux31.IN8 -op[1] => Mux0.IN7 -op[1] => Mux1.IN7 -op[1] => Mux2.IN7 -op[1] => Mux3.IN7 -op[1] => Mux4.IN7 -op[1] => Mux5.IN7 -op[1] => Mux6.IN7 -op[1] => Mux7.IN7 -op[1] => Mux8.IN7 -op[1] => Mux9.IN7 -op[1] => Mux10.IN7 -op[1] => Mux11.IN7 -op[1] => Mux12.IN7 -op[1] => Mux13.IN7 -op[1] => Mux14.IN7 -op[1] => Mux15.IN7 -op[1] => Mux16.IN7 -op[1] => Mux17.IN7 -op[1] => Mux18.IN7 -op[1] => Mux19.IN7 -op[1] => Mux20.IN7 -op[1] => Mux21.IN7 -op[1] => Mux22.IN7 -op[1] => Mux23.IN7 -op[1] => Mux24.IN7 -op[1] => Mux25.IN7 -op[1] => Mux26.IN7 -op[1] => Mux27.IN7 -op[1] => Mux28.IN7 -op[1] => Mux29.IN7 -op[1] => Mux30.IN7 -op[1] => Mux31.IN7 -op[2] => Mux0.IN6 -op[2] => Mux1.IN6 -op[2] => Mux2.IN6 -op[2] => Mux3.IN6 -op[2] => Mux4.IN6 -op[2] => Mux5.IN6 -op[2] => Mux6.IN6 -op[2] => Mux7.IN6 -op[2] => Mux8.IN6 -op[2] => Mux9.IN6 -op[2] => Mux10.IN6 -op[2] => Mux11.IN6 -op[2] => Mux12.IN6 -op[2] => Mux13.IN6 -op[2] => Mux14.IN6 -op[2] => Mux15.IN6 -op[2] => Mux16.IN6 -op[2] => Mux17.IN6 -op[2] => Mux18.IN6 -op[2] => Mux19.IN6 -op[2] => Mux20.IN6 -op[2] => Mux21.IN6 -op[2] => Mux22.IN6 -op[2] => Mux23.IN6 -op[2] => Mux24.IN6 -op[2] => Mux25.IN6 -op[2] => Mux26.IN6 -op[2] => Mux27.IN6 -op[2] => Mux28.IN6 -op[2] => Mux29.IN6 -op[2] => Mux30.IN6 -op[2] => Mux31.IN6 -A[0] => ShiftLeft0.IN32 -A[0] => ShiftRight0.IN32 -A[0] => ShiftRight1.IN32 -A[0] => ShiftLeft1.IN32 -A[0] => ShiftRight2.IN32 -A[0] => ShiftRight3.IN32 -A[0] => Mux31.IN9 -A[0] => Mux31.IN10 -A[1] => ShiftLeft0.IN31 -A[1] => ShiftRight0.IN31 -A[1] => ShiftRight1.IN31 -A[1] => ShiftLeft1.IN31 -A[1] => ShiftRight2.IN31 -A[1] => ShiftRight3.IN31 -A[1] => Mux30.IN9 -A[1] => Mux30.IN10 -A[2] => ShiftLeft0.IN30 -A[2] => ShiftRight0.IN30 -A[2] => ShiftRight1.IN30 -A[2] => ShiftLeft1.IN30 -A[2] => ShiftRight2.IN30 -A[2] => ShiftRight3.IN30 -A[2] => Mux29.IN9 -A[2] => Mux29.IN10 -A[3] => ShiftLeft0.IN29 -A[3] => ShiftRight0.IN29 -A[3] => ShiftRight1.IN29 -A[3] => ShiftLeft1.IN29 -A[3] => ShiftRight2.IN29 -A[3] => ShiftRight3.IN29 -A[3] => Mux28.IN9 -A[3] => Mux28.IN10 -A[4] => ShiftLeft0.IN28 -A[4] => ShiftRight0.IN28 -A[4] => ShiftRight1.IN28 -A[4] => ShiftLeft1.IN28 -A[4] => ShiftRight2.IN28 -A[4] => ShiftRight3.IN28 -A[4] => Mux27.IN9 -A[4] => Mux27.IN10 -A[5] => ShiftLeft0.IN27 -A[5] => ShiftRight0.IN27 -A[5] => ShiftRight1.IN27 -A[5] => ShiftLeft1.IN27 -A[5] => ShiftRight2.IN27 -A[5] => ShiftRight3.IN27 -A[5] => Mux26.IN9 -A[5] => Mux26.IN10 -A[6] => ShiftLeft0.IN26 -A[6] => ShiftRight0.IN26 -A[6] => ShiftRight1.IN26 -A[6] => ShiftLeft1.IN26 -A[6] => ShiftRight2.IN26 -A[6] => ShiftRight3.IN26 -A[6] => Mux25.IN9 -A[6] => Mux25.IN10 -A[7] => ShiftLeft0.IN25 -A[7] => ShiftRight0.IN25 -A[7] => ShiftRight1.IN25 -A[7] => ShiftLeft1.IN25 -A[7] => ShiftRight2.IN25 -A[7] => ShiftRight3.IN25 -A[7] => Mux24.IN9 -A[7] => Mux24.IN10 -A[8] => ShiftLeft0.IN24 -A[8] => ShiftRight0.IN24 -A[8] => ShiftRight1.IN24 -A[8] => ShiftLeft1.IN24 -A[8] => ShiftRight2.IN24 -A[8] => ShiftRight3.IN24 -A[8] => Mux23.IN9 -A[8] => Mux23.IN10 -A[9] => ShiftLeft0.IN23 -A[9] => ShiftRight0.IN23 -A[9] => ShiftRight1.IN23 -A[9] => ShiftLeft1.IN23 -A[9] => ShiftRight2.IN23 -A[9] => ShiftRight3.IN23 -A[9] => Mux22.IN9 -A[9] => Mux22.IN10 -A[10] => ShiftLeft0.IN22 -A[10] => ShiftRight0.IN22 -A[10] => ShiftRight1.IN22 -A[10] => ShiftLeft1.IN22 -A[10] => ShiftRight2.IN22 -A[10] => ShiftRight3.IN22 -A[10] => Mux21.IN9 -A[10] => Mux21.IN10 -A[11] => ShiftLeft0.IN21 -A[11] => ShiftRight0.IN21 -A[11] => ShiftRight1.IN21 -A[11] => ShiftLeft1.IN21 -A[11] => ShiftRight2.IN21 -A[11] => ShiftRight3.IN21 -A[11] => Mux20.IN9 -A[11] => Mux20.IN10 -A[12] => ShiftLeft0.IN20 -A[12] => ShiftRight0.IN20 -A[12] => ShiftRight1.IN20 -A[12] => ShiftLeft1.IN20 -A[12] => ShiftRight2.IN20 -A[12] => ShiftRight3.IN20 -A[12] => Mux19.IN9 -A[12] => Mux19.IN10 -A[13] => ShiftLeft0.IN19 -A[13] => ShiftRight0.IN19 -A[13] => ShiftRight1.IN19 -A[13] => ShiftLeft1.IN19 -A[13] => ShiftRight2.IN19 -A[13] => ShiftRight3.IN19 -A[13] => Mux18.IN9 -A[13] => Mux18.IN10 -A[14] => ShiftLeft0.IN18 -A[14] => ShiftRight0.IN18 -A[14] => ShiftRight1.IN18 -A[14] => ShiftLeft1.IN18 -A[14] => ShiftRight2.IN18 -A[14] => ShiftRight3.IN18 -A[14] => Mux17.IN9 -A[14] => Mux17.IN10 -A[15] => ShiftLeft0.IN17 -A[15] => ShiftRight0.IN17 -A[15] => ShiftRight1.IN17 -A[15] => ShiftLeft1.IN17 -A[15] => ShiftRight2.IN17 -A[15] => ShiftRight3.IN17 -A[15] => Mux16.IN9 -A[15] => Mux16.IN10 -A[16] => ShiftLeft0.IN16 -A[16] => ShiftRight0.IN16 -A[16] => ShiftRight1.IN16 -A[16] => ShiftLeft1.IN16 -A[16] => ShiftRight2.IN16 -A[16] => ShiftRight3.IN16 -A[16] => Mux15.IN9 -A[16] => Mux15.IN10 -A[17] => ShiftLeft0.IN15 -A[17] => ShiftRight0.IN15 -A[17] => ShiftRight1.IN15 -A[17] => ShiftLeft1.IN15 -A[17] => ShiftRight2.IN15 -A[17] => ShiftRight3.IN15 -A[17] => Mux14.IN9 -A[17] => Mux14.IN10 -A[18] => ShiftLeft0.IN14 -A[18] => ShiftRight0.IN14 -A[18] => ShiftRight1.IN14 -A[18] => ShiftLeft1.IN14 -A[18] => ShiftRight2.IN14 -A[18] => ShiftRight3.IN14 -A[18] => Mux13.IN9 -A[18] => Mux13.IN10 -A[19] => ShiftLeft0.IN13 -A[19] => ShiftRight0.IN13 -A[19] => ShiftRight1.IN13 -A[19] => ShiftLeft1.IN13 -A[19] => ShiftRight2.IN13 -A[19] => ShiftRight3.IN13 -A[19] => Mux12.IN9 -A[19] => Mux12.IN10 -A[20] => ShiftLeft0.IN12 -A[20] => ShiftRight0.IN12 -A[20] => ShiftRight1.IN12 -A[20] => ShiftLeft1.IN12 -A[20] => ShiftRight2.IN12 -A[20] => ShiftRight3.IN12 -A[20] => Mux11.IN9 -A[20] => Mux11.IN10 -A[21] => ShiftLeft0.IN11 -A[21] => ShiftRight0.IN11 -A[21] => ShiftRight1.IN11 -A[21] => ShiftLeft1.IN11 -A[21] => ShiftRight2.IN11 -A[21] => ShiftRight3.IN11 -A[21] => Mux10.IN9 -A[21] => Mux10.IN10 -A[22] => ShiftLeft0.IN10 -A[22] => ShiftRight0.IN10 -A[22] => ShiftRight1.IN10 -A[22] => ShiftLeft1.IN10 -A[22] => ShiftRight2.IN10 -A[22] => ShiftRight3.IN10 -A[22] => Mux9.IN9 -A[22] => Mux9.IN10 -A[23] => ShiftLeft0.IN9 -A[23] => ShiftRight0.IN9 -A[23] => ShiftRight1.IN9 -A[23] => ShiftLeft1.IN9 -A[23] => ShiftRight2.IN9 -A[23] => ShiftRight3.IN9 -A[23] => Mux8.IN9 -A[23] => Mux8.IN10 -A[24] => ShiftLeft0.IN8 -A[24] => ShiftRight0.IN8 -A[24] => ShiftRight1.IN8 -A[24] => ShiftLeft1.IN8 -A[24] => ShiftRight2.IN8 -A[24] => ShiftRight3.IN8 -A[24] => Mux7.IN9 -A[24] => Mux7.IN10 -A[25] => ShiftLeft0.IN7 -A[25] => ShiftRight0.IN7 -A[25] => ShiftRight1.IN7 -A[25] => ShiftLeft1.IN7 -A[25] => ShiftRight2.IN7 -A[25] => ShiftRight3.IN7 -A[25] => Mux6.IN9 -A[25] => Mux6.IN10 -A[26] => ShiftLeft0.IN6 -A[26] => ShiftRight0.IN6 -A[26] => ShiftRight1.IN6 -A[26] => ShiftLeft1.IN6 -A[26] => ShiftRight2.IN6 -A[26] => ShiftRight3.IN6 -A[26] => Mux5.IN9 -A[26] => Mux5.IN10 -A[27] => ShiftLeft0.IN5 -A[27] => ShiftRight0.IN5 -A[27] => ShiftRight1.IN5 -A[27] => ShiftLeft1.IN5 -A[27] => ShiftRight2.IN5 -A[27] => ShiftRight3.IN5 -A[27] => Mux4.IN9 -A[27] => Mux4.IN10 -A[28] => ShiftLeft0.IN4 -A[28] => ShiftRight0.IN4 -A[28] => ShiftRight1.IN4 -A[28] => ShiftLeft1.IN4 -A[28] => ShiftRight2.IN4 -A[28] => ShiftRight3.IN4 -A[28] => Mux3.IN9 -A[28] => Mux3.IN10 -A[29] => ShiftLeft0.IN3 -A[29] => ShiftRight0.IN3 -A[29] => ShiftRight1.IN3 -A[29] => ShiftLeft1.IN3 -A[29] => ShiftRight2.IN3 -A[29] => ShiftRight3.IN3 -A[29] => Mux2.IN9 -A[29] => Mux2.IN10 -A[30] => ShiftLeft0.IN2 -A[30] => ShiftRight0.IN2 -A[30] => ShiftRight1.IN2 -A[30] => ShiftLeft1.IN2 -A[30] => ShiftRight2.IN2 -A[30] => ShiftRight3.IN2 -A[30] => Mux1.IN9 -A[30] => Mux1.IN10 -A[31] => ShiftLeft0.IN1 -A[31] => ShiftRight0.IN1 -A[31] => ShiftRight1.IN0 -A[31] => ShiftRight1.IN1 -A[31] => ShiftLeft1.IN1 -A[31] => ShiftRight2.IN1 -A[31] => ShiftRight3.IN0 -A[31] => ShiftRight3.IN1 -A[31] => Mux0.IN9 -A[31] => Mux0.IN10 -B[0] => ShiftLeft1.IN64 -B[0] => ShiftRight2.IN64 -B[0] => ShiftRight3.IN64 -B[1] => ShiftLeft1.IN63 -B[1] => ShiftRight2.IN63 -B[1] => ShiftRight3.IN63 -B[2] => ShiftLeft1.IN62 -B[2] => ShiftRight2.IN62 -B[2] => ShiftRight3.IN62 -B[3] => ShiftLeft1.IN61 -B[3] => ShiftRight2.IN61 -B[3] => ShiftRight3.IN61 -B[4] => ShiftLeft1.IN60 -B[4] => ShiftRight2.IN60 -B[4] => ShiftRight3.IN60 -B[5] => ShiftLeft1.IN59 -B[5] => ShiftRight2.IN59 -B[5] => ShiftRight3.IN59 -B[6] => ShiftLeft1.IN58 -B[6] => ShiftRight2.IN58 -B[6] => ShiftRight3.IN58 -B[7] => ShiftLeft1.IN57 -B[7] => ShiftRight2.IN57 -B[7] => ShiftRight3.IN57 -B[8] => ShiftLeft1.IN56 -B[8] => ShiftRight2.IN56 -B[8] => ShiftRight3.IN56 -B[9] => ShiftLeft1.IN55 -B[9] => ShiftRight2.IN55 -B[9] => ShiftRight3.IN55 -B[10] => ShiftLeft1.IN54 -B[10] => ShiftRight2.IN54 -B[10] => ShiftRight3.IN54 -B[11] => ShiftLeft1.IN53 -B[11] => ShiftRight2.IN53 -B[11] => ShiftRight3.IN53 -B[12] => ShiftLeft1.IN52 -B[12] => ShiftRight2.IN52 -B[12] => ShiftRight3.IN52 -B[13] => ShiftLeft1.IN51 -B[13] => ShiftRight2.IN51 -B[13] => ShiftRight3.IN51 -B[14] => ShiftLeft1.IN50 -B[14] => ShiftRight2.IN50 -B[14] => ShiftRight3.IN50 -B[15] => ShiftLeft1.IN49 -B[15] => ShiftRight2.IN49 -B[15] => ShiftRight3.IN49 -B[16] => ShiftLeft1.IN48 -B[16] => ShiftRight2.IN48 -B[16] => ShiftRight3.IN48 -B[17] => ShiftLeft1.IN47 -B[17] => ShiftRight2.IN47 -B[17] => ShiftRight3.IN47 -B[18] => ShiftLeft1.IN46 -B[18] => ShiftRight2.IN46 -B[18] => ShiftRight3.IN46 -B[19] => ShiftLeft1.IN45 -B[19] => ShiftRight2.IN45 -B[19] => ShiftRight3.IN45 -B[20] => ShiftLeft1.IN44 -B[20] => ShiftRight2.IN44 -B[20] => ShiftRight3.IN44 -B[21] => ShiftLeft1.IN43 -B[21] => ShiftRight2.IN43 -B[21] => ShiftRight3.IN43 -B[22] => ShiftLeft1.IN42 -B[22] => ShiftRight2.IN42 -B[22] => ShiftRight3.IN42 -B[23] => ShiftLeft1.IN41 -B[23] => ShiftRight2.IN41 -B[23] => ShiftRight3.IN41 -B[24] => ShiftLeft1.IN40 -B[24] => ShiftRight2.IN40 -B[24] => ShiftRight3.IN40 -B[25] => ShiftLeft1.IN39 -B[25] => ShiftRight2.IN39 -B[25] => ShiftRight3.IN39 -B[26] => ShiftLeft1.IN38 -B[26] => ShiftRight2.IN38 -B[26] => ShiftRight3.IN38 -B[27] => ShiftLeft1.IN37 -B[27] => ShiftRight2.IN37 -B[27] => ShiftRight3.IN37 -B[28] => ShiftLeft1.IN36 -B[28] => ShiftRight2.IN36 -B[28] => ShiftRight3.IN36 -B[29] => ShiftLeft1.IN35 -B[29] => ShiftRight2.IN35 -B[29] => ShiftRight3.IN35 -B[30] => ShiftLeft1.IN34 -B[30] => ShiftRight2.IN34 -B[30] => ShiftRight3.IN34 -B[31] => ShiftLeft1.IN33 -B[31] => ShiftRight2.IN33 -B[31] => ShiftRight3.IN33 -C[0] => ShiftLeft0.IN37 -C[0] => ShiftRight0.IN37 -C[0] => ShiftRight1.IN37 -C[1] => ShiftLeft0.IN36 -C[1] => ShiftRight0.IN36 -C[1] => ShiftRight1.IN36 -C[2] => ShiftLeft0.IN35 -C[2] => ShiftRight0.IN35 -C[2] => ShiftRight1.IN35 -C[3] => ShiftLeft0.IN34 -C[3] => ShiftRight0.IN34 -C[3] => ShiftRight1.IN34 -C[4] => ShiftLeft0.IN33 -C[4] => ShiftRight0.IN33 -C[4] => ShiftRight1.IN33 -OUT_1[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE - - |assignment2|seven_seg_4digit:display num[0] => num[0].IN1 num[1] => num[1].IN1 diff --git a/Quartus/A2/db/assignment2.hif b/Quartus/A2/db/assignment2.hif index 0d02521..f4d85e2 100644 Binary files a/Quartus/A2/db/assignment2.hif and b/Quartus/A2/db/assignment2.hif differ diff --git a/Quartus/A2/db/assignment2.lpc.html b/Quartus/A2/db/assignment2.lpc.html index 8459bf3..db7f511 100644 --- a/Quartus/A2/db/assignment2.lpc.html +++ b/Quartus/A2/db/assignment2.lpc.html @@ -82,31 +82,15 @@ display 16 -16 0 -16 +0 +0 32 -16 -16 -16 0 0 0 0 0 - - -SHIFTER -72 -27 -0 -27 -32 -27 -27 -27 -0 -0 0 0 0 @@ -146,13 +130,29 @@ ALU 68 +1 +0 +1 +35 +1 +1 +1 0 0 0 -34 0 0 + + +SIGNEXT +17 +15 0 +15 +32 +15 +15 +15 0 0 0 @@ -165,7 +165,7 @@ 0 0 0 -32 +1088 0 0 0 @@ -176,23 +176,7 @@ 0 -INSTRUCTION_MODULE_CLASSIFIER -3 -0 -0 -0 -4 -0 -0 -0 -0 -0 -0 -0 -0 - - -INSTRUCTION_CLASSIFIER +CONTROL_UNIT|CLASSIFIER 6 0 0 @@ -208,6 +192,38 @@ 0 +CONTROL_UNIT +12 +0 +2 +0 +10 +0 +0 +0 +0 +0 +0 +0 +0 + + +RAM +546 +510 +51 +510 +32 +510 +510 +510 +0 +0 +0 +0 +0 + + ROM 10 0 diff --git a/Quartus/A2/db/assignment2.lpc.rdb b/Quartus/A2/db/assignment2.lpc.rdb index 611a5f3..50430f0 100644 Binary files a/Quartus/A2/db/assignment2.lpc.rdb and b/Quartus/A2/db/assignment2.lpc.rdb differ diff --git a/Quartus/A2/db/assignment2.lpc.txt b/Quartus/A2/db/assignment2.lpc.txt index 6db1c5f..6e7d9da 100644 --- a/Quartus/A2/db/assignment2.lpc.txt +++ b/Quartus/A2/db/assignment2.lpc.txt @@ -1,20 +1,21 @@ -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+-------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+-------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; display|digit3 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; display|digit2 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; display|digit1 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; display|digit0 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; display ; 16 ; 16 ; 0 ; 16 ; 32 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; SHIFTER ; 72 ; 27 ; 0 ; 27 ; 32 ; 27 ; 27 ; 27 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; ALU|logic_unit ; 66 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; ALU|adder_unit ; 65 ; 0 ; 0 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; ALU ; 68 ; 0 ; 0 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; REGS ; 49 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; INSTRUCTION_MODULE_CLASSIFIER ; 3 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; INSTRUCTION_CLASSIFIER ; 6 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; ROM ; 10 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; PC ; 34 ; 44 ; 0 ; 44 ; 32 ; 44 ; 44 ; 44 ; 0 ; 0 ; 0 ; 0 ; 0 ; -+-------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; display|digit3 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; display|digit2 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; display|digit1 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; display|digit0 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; display ; 16 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; ALU|logic_unit ; 66 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; ALU|adder_unit ; 65 ; 0 ; 0 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; ALU ; 68 ; 1 ; 0 ; 1 ; 35 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; SIGNEXT ; 17 ; 15 ; 0 ; 15 ; 32 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; REGS ; 49 ; 0 ; 0 ; 0 ; 1088 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CONTROL_UNIT|CLASSIFIER ; 6 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CONTROL_UNIT ; 12 ; 0 ; 2 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; RAM ; 546 ; 510 ; 51 ; 510 ; 32 ; 510 ; 510 ; 510 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; ROM ; 10 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; PC ; 34 ; 44 ; 0 ; 44 ; 32 ; 44 ; 44 ; 44 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/Quartus/A2/db/assignment2.map.bpm b/Quartus/A2/db/assignment2.map.bpm new file mode 100644 index 0000000..47f98b4 Binary files /dev/null and b/Quartus/A2/db/assignment2.map.bpm differ diff --git a/Quartus/A2/db/assignment2.map.cdb b/Quartus/A2/db/assignment2.map.cdb new file mode 100644 index 0000000..f586487 Binary files /dev/null and b/Quartus/A2/db/assignment2.map.cdb differ diff --git a/Quartus/A2/db/assignment2.map.hdb b/Quartus/A2/db/assignment2.map.hdb new file mode 100644 index 0000000..6bddb95 Binary files /dev/null and b/Quartus/A2/db/assignment2.map.hdb differ diff --git a/Quartus/A2/db/assignment2.map.kpt b/Quartus/A2/db/assignment2.map.kpt index 59be3a1..f96647a 100644 Binary files a/Quartus/A2/db/assignment2.map.kpt and b/Quartus/A2/db/assignment2.map.kpt differ diff --git a/Quartus/A2/db/assignment2.map.logdb b/Quartus/A2/db/assignment2.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/Quartus/A2/db/assignment2.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/Quartus/A2/db/assignment2.map.qmsg b/Quartus/A2/db/assignment2.map.qmsg index 107732a..ab4fc5c 100644 --- a/Quartus/A2/db/assignment2.map.qmsg +++ b/Quartus/A2/db/assignment2.map.qmsg @@ -1,24 +1,37 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792037050413 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792037050419 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 15 15:04:10 2026 " "Processing started: Thu Oct 15 15:04:10 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792037050419 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037050419 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037050420 ""} -{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792037050731 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037059808 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792037059945 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 assignment2.sv(100) " "Verilog HDL assignment warning at assignment2.sv(100): truncated value with size 32 to match size of target (10)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792037059951 "|assignment2"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "flags\[2\] 0 assignment2.sv(55) " "Net \"flags\[2\]\" at assignment2.sv(55) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 55 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792037059954 "|assignment2"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 62 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037059972 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 64 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037059977 ""} -{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1792037059990 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792037060027 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792037060027 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792037060027 "|assignment2|rom:ROM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram ram:RAM " "Elaborating entity \"ram\" for hierarchy \"ram:RAM\"" { } { { "../../modules/assignment2.sv" "RAM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 67 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060031 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ram.sv(23) " "Verilog HDL assignment warning at ram.sv(23): truncated value with size 32 to match size of target (8)" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 23 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792037060808 "|assignment2|ram:RAM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 69 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060822 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 76 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060825 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060828 ""} -{ "Warning" "WVRFX_VERI_2116_UNCONVERTED" "regs register_file.sv(14) " "Verilog HDL warning at register_file.sv(14): initial value for variable regs should be constant" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 14 0 0 } } } 0 10855 "Verilog HDL warning at %2!s!: initial value for variable %1!s! should be constant" 0 0 "Analysis & Synthesis" 0 -1 1792037060829 "|assignment2|register_file:REGS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_extender sign_extender:SIGNEXT " "Elaborating entity \"sign_extender\" for hierarchy \"sign_extender:SIGNEXT\"" { } { { "../../modules/assignment2.sv" "SIGNEXT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 88 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060943 ""} -{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT" "sign_extender.sv(11) " "Verilog HDL unsupported feature error at sign_extender.sv(11): Procedural Continuous Assignment to register is not supported" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 11 0 0 } } } 0 10043 "Verilog HDL unsupported feature error at %1!s!: Procedural Continuous Assignment to register is not supported" 0 0 "Analysis & Synthesis" 0 -1 1792037060943 ""} -{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "sign_extender:SIGNEXT " "Can't elaborate user hierarchy \"sign_extender:SIGNEXT\"" { } { { "../../modules/assignment2.sv" "SIGNEXT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 88 0 0 } } } 0 12152 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060943 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 8 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 8 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792037061004 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 15 15:04:21 2026 " "Processing ended: Thu Oct 15 15:04:21 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792037061004 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792037061004 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792037061004 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037061004 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792105086550 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792105086551 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 16 09:58:06 2026 " "Processing started: Fri Oct 16 09:58:06 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792105086551 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792105086551 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792105086551 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792105086872 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "6 control_unit " "Found entity 6: control_unit" { } { { "../../modules/control_unit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792105095944 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792105096087 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 assignment2.sv(87) " "Verilog HDL assignment warning at assignment2.sv(87): truncated value with size 32 to match size of target (10)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 87 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792105096098 "|assignment2"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "flags\[2\] 0 assignment2.sv(48) " "Net \"flags\[2\]\" at assignment2.sv(48) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 48 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792105096098 "|assignment2"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096099 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096107 ""} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1792105096118 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792105096162 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792105096162 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792105096162 "|assignment2|rom:ROM"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram ram:RAM " "Elaborating entity \"ram\" for hierarchy \"ram:RAM\"" { } { { "../../modules/assignment2.sv" "RAM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 60 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096167 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 2 ram.sv(18) " "Verilog HDL assignment warning at ram.sv(18): truncated value with size 8 to match size of target (2)" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792105096168 "|assignment2|ram:RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 ram.sv(24) " "Verilog HDL assignment warning at ram.sv(24): truncated value with size 32 to match size of target (2)" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792105096915 "|assignment2|ram:RAM"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_unit control_unit:CONTROL_UNIT " "Elaborating entity \"control_unit\" for hierarchy \"control_unit:CONTROL_UNIT\"" { } { { "../../modules/assignment2.sv" "CONTROL_UNIT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 64 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096923 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 control_unit.sv(29) " "Verilog HDL assignment warning at control_unit.sv(29): truncated value with size 6 to match size of target (4)" { } { { "../../modules/control_unit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 29 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792105096924 "|assignment2|control_unit:CONTROL_UNIT"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier control_unit:CONTROL_UNIT\|instruction_classifier:CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"control_unit:CONTROL_UNIT\|instruction_classifier:CLASSIFIER\"" { } { { "../../modules/control_unit.sv" "CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 23 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096928 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 73 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096932 ""} +{ "Warning" "WVRFX_VERI_2116_UNCONVERTED" "regs register_file.sv(14) " "Verilog HDL warning at register_file.sv(14): initial value for variable regs should be constant" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 14 0 0 } } } 0 10855 "Verilog HDL warning at %2!s!: initial value for variable %1!s! should be constant" 0 0 "Analysis & Synthesis" 0 -1 1792105096934 "|assignment2|register_file:REGS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_extender sign_extender:SIGNEXT " "Elaborating entity \"sign_extender\" for hierarchy \"sign_extender:SIGNEXT\"" { } { { "../../modules/assignment2.sv" "SIGNEXT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 76 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097052 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097055 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097062 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097068 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_4digit seven_seg_4digit:display " "Elaborating entity \"seven_seg_4digit\" for hierarchy \"seven_seg_4digit:display\"" { } { { "../../modules/assignment2.sv" "display" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 104 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097074 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg_4digit:display\|seven_seg:digit0 " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg_4digit:display\|seven_seg:digit0\"" { } { { "../../modules/seven_seg_4digit.sv" "digit0" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097077 ""} +{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "1 " "Found 1 instances of uninferred RAM logic" { { "Info" "IINFER_READ_LOGIC_IS_ASYNCHRONOUS" "ram:RAM\|mem " "RAM logic \"ram:RAM\|mem\" is uninferred due to asynchronous read logic" { } { { "../../modules/ram.sv" "mem" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 13 -1 0 } } } 0 276007 "RAM logic \"%1!s!\" is uninferred due to asynchronous read logic" 0 0 "Design Software" 0 -1 1792105097741 ""} } { } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1792105097741 ""} +{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/db/assignment2.ram0_rom_d8639f5.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/db/assignment2.ram0_rom_d8639f5.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" { } { } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1792105097774 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1792105098851 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[0\] VCC " "Pin \"out_seg_0\[0\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[1\] VCC " "Pin \"out_seg_0\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[2\] VCC " "Pin \"out_seg_0\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[3\] VCC " "Pin \"out_seg_0\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[4\] VCC " "Pin \"out_seg_0\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[5\] VCC " "Pin \"out_seg_0\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[6\] VCC " "Pin \"out_seg_0\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[7\] VCC " "Pin \"out_seg_0\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[0\] VCC " "Pin \"out_seg_1\[0\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[1\] VCC " "Pin \"out_seg_1\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[2\] VCC " "Pin \"out_seg_1\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[3\] VCC " "Pin \"out_seg_1\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[4\] VCC " "Pin \"out_seg_1\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[5\] VCC " "Pin \"out_seg_1\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[6\] VCC " "Pin \"out_seg_1\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[7\] VCC " "Pin \"out_seg_1\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[0\] VCC " "Pin \"out_seg_2\[0\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[1\] VCC " "Pin \"out_seg_2\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[2\] VCC " "Pin \"out_seg_2\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[3\] VCC " "Pin \"out_seg_2\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[4\] VCC " "Pin \"out_seg_2\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[5\] VCC " "Pin \"out_seg_2\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[6\] VCC " "Pin \"out_seg_2\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_2[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[7\] VCC " "Pin \"out_seg_2\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_2[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[0\] VCC " "Pin \"out_seg_3\[0\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_3[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[1\] VCC " "Pin \"out_seg_3\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[2\] VCC " "Pin \"out_seg_3\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[3\] VCC " "Pin \"out_seg_3\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_3[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[4\] VCC " "Pin \"out_seg_3\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_3[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[5\] VCC " "Pin \"out_seg_3\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_3[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[6\] VCC " "Pin \"out_seg_3\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[7\] VCC " "Pin \"out_seg_3\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_3[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1792105098866 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "30 " "30 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1792105098892 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1792105099101 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105099101 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_PC\[0\] " "No output dependent on input pin \"HID_PC\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 20 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_PC[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Hi_Low\[0\] " "No output dependent on input pin \"HID_Hi_Low\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Hi_Low[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[4\] " "No output dependent on input pin \"HID_Register\[4\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[2\] " "No output dependent on input pin \"HID_Register\[2\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[0\] " "No output dependent on input pin \"HID_Register\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[1\] " "No output dependent on input pin \"HID_Register\[1\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[3\] " "No output dependent on input pin \"HID_Register\[3\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|clk[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1792105099207 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1792105099208 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1792105099208 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1792105099208 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 54 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 54 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "440 " "Peak virtual memory: 440 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792105099231 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 16 09:58:19 2026 " "Processing ended: Fri Oct 16 09:58:19 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792105099231 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792105099231 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792105099231 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792105099231 ""} diff --git a/Quartus/A2/db/assignment2.map.rdb b/Quartus/A2/db/assignment2.map.rdb index a3ab763..d6dc3f1 100644 Binary files a/Quartus/A2/db/assignment2.map.rdb and b/Quartus/A2/db/assignment2.map.rdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.cdb b/Quartus/A2/db/assignment2.map_bb.cdb new file mode 100644 index 0000000..942adeb Binary files /dev/null and b/Quartus/A2/db/assignment2.map_bb.cdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.hdb b/Quartus/A2/db/assignment2.map_bb.hdb index 587199c..e0c61d3 100644 Binary files a/Quartus/A2/db/assignment2.map_bb.hdb and b/Quartus/A2/db/assignment2.map_bb.hdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.logdb b/Quartus/A2/db/assignment2.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/Quartus/A2/db/assignment2.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/Quartus/A2/db/assignment2.pre_map.hdb b/Quartus/A2/db/assignment2.pre_map.hdb index 6f1af80..7d3da6c 100644 Binary files a/Quartus/A2/db/assignment2.pre_map.hdb and b/Quartus/A2/db/assignment2.pre_map.hdb differ diff --git a/Quartus/A2/db/assignment2.quiproj.4395.rdr.flock b/Quartus/A2/db/assignment2.quiproj.4395.rdr.flock deleted file mode 100644 index e69de29..0000000 diff --git a/Quartus/A2/db/assignment2.ram0_ram_d7e4eb10.hdl.mif b/Quartus/A2/db/assignment2.ram0_ram_d7e4eb10.hdl.mif index 8c09a91..9ba161b 100644 --- a/Quartus/A2/db/assignment2.ram0_ram_d7e4eb10.hdl.mif +++ b/Quartus/A2/db/assignment2.ram0_ram_d7e4eb10.hdl.mif @@ -4,2059 +4,2059 @@ -- datawidth -- 32) -- end_signature -WIDTH=8; +WIDTH=2; DEPTH=2048; ADDRESS_RADIX=UNS; DATA_RADIX=BIN; CONTENT BEGIN - 2047 : 00000000; - 2046 : 00000000; - 2045 : 00000000; - 2044 : 00000000; - 2043 : 00000000; - 2042 : 00000000; - 2041 : 00000000; - 2040 : 00000000; - 2039 : 00000000; - 2038 : 00000000; - 2037 : 00000000; - 2036 : 00000000; - 2035 : 00000000; - 2034 : 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00; + 11 : 00; + 10 : 00; + 9 : 00; + 8 : 00; + 7 : 00; + 6 : 00; + 5 : 00; + 4 : 00; + 3 : 00; + 2 : 00; + 1 : 00; + 0 : 00; END; diff --git a/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb b/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb index b9d1fed..843d689 100644 Binary files a/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb and b/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb differ diff --git a/Quartus/A2/db/assignment2.rtlv.hdb b/Quartus/A2/db/assignment2.rtlv.hdb index b868141..48c264b 100644 Binary files a/Quartus/A2/db/assignment2.rtlv.hdb and b/Quartus/A2/db/assignment2.rtlv.hdb differ diff --git a/Quartus/A2/db/assignment2.rtlv_sg.cdb b/Quartus/A2/db/assignment2.rtlv_sg.cdb index 86ef8de..220fd40 100644 Binary files a/Quartus/A2/db/assignment2.rtlv_sg.cdb and b/Quartus/A2/db/assignment2.rtlv_sg.cdb differ diff --git a/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb b/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb index 679831e..6a5f81f 100644 Binary files a/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb and b/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb differ diff --git a/Quartus/A2/db/assignment2.smart_action.txt b/Quartus/A2/db/assignment2.smart_action.txt index 11b531f..c8e8a13 100644 --- a/Quartus/A2/db/assignment2.smart_action.txt +++ b/Quartus/A2/db/assignment2.smart_action.txt @@ -1 +1 @@ -SOURCE +DONE diff --git a/Quartus/A2/db/assignment2.sta.qmsg b/Quartus/A2/db/assignment2.sta.qmsg index 96f5912..866a77d 100644 --- a/Quartus/A2/db/assignment2.sta.qmsg +++ b/Quartus/A2/db/assignment2.sta.qmsg @@ -1,60 +1,60 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791870494616 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791870494617 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:48:14 2026 " "Processing started: Tue Oct 13 16:48:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791870494617 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1791870494617 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta assignment2 -c assignment2 " "Command: quartus_sta assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1791870494617 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1791870494671 ""} -{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1791870495176 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870495246 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870495246 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1791870495827 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870495827 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791870495828 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791870495828 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1791870495828 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791870495829 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1791870495829 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1791870495834 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791870495834 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495835 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495839 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495840 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495840 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495841 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870495842 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791870495844 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791870495888 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791870496882 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870496981 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791870496981 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791870496982 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791870496982 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496983 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496984 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496985 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496986 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496986 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870496987 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791870496989 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791870497237 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791870497794 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870497852 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791870497852 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791870497852 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791870497853 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497854 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497856 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497857 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497858 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870497859 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791870497862 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791870498013 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791870498013 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791870498013 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791870498013 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498014 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498015 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498016 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498017 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791870498017 ""} -{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791870499645 ""} -{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791870499646 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "761 " "Peak virtual memory: 761 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791870499676 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:48:19 2026 " "Processing ended: Tue Oct 13 16:48:19 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791870499676 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791870499676 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791870499676 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1791870499676 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792105137783 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792105137783 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 16 09:58:57 2026 " "Processing started: Fri Oct 16 09:58:57 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792105137783 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1792105137783 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta assignment2 -c assignment2 " "Command: quartus_sta assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1792105137783 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1792105137844 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1792105138346 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1792105138416 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1792105138416 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1792105138989 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1792105138990 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1792105138990 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1792105138990 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1792105138991 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1792105138991 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1792105138991 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1792105138998 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1792105138999 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105139000 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105139003 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105139004 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105139005 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105139006 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105139006 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1792105139008 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1792105139053 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1792105140053 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1792105140144 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1792105140144 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1792105140145 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1792105140145 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105140146 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105140147 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105140148 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105140149 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105140149 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105140150 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1792105140152 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1792105140395 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1792105140964 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1792105141005 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1792105141005 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1792105141005 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1792105141005 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141006 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141007 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141008 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141009 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141009 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1792105141011 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1792105141157 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1792105141157 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1792105141157 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1792105141158 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141159 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141160 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141160 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141161 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1792105141162 ""} +{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1792105142807 ""} +{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1792105142808 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "765 " "Peak virtual memory: 765 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792105142843 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 16 09:59:02 2026 " "Processing ended: Fri Oct 16 09:59:02 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792105142843 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792105142843 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792105142843 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1792105142843 ""} diff --git a/Quartus/A2/db/assignment2.sta.rdb b/Quartus/A2/db/assignment2.sta.rdb index 7a3b4ed..134da9b 100644 Binary files a/Quartus/A2/db/assignment2.sta.rdb and b/Quartus/A2/db/assignment2.sta.rdb differ diff --git a/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb new file mode 100644 index 0000000..bcfe174 Binary files /dev/null and b/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A2/db/assignment2.tis_db_list.ddb b/Quartus/A2/db/assignment2.tis_db_list.ddb index 7ff9e34..06ddd4e 100644 Binary files a/Quartus/A2/db/assignment2.tis_db_list.ddb and b/Quartus/A2/db/assignment2.tis_db_list.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb index 19f4958..b99e4bb 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb index fa9fc18..0de6228 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb index 6f0c000..7f4ce89 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb index 35dcd02..8992b21 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb index b14f66a..860a340 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb index 8ffeed4..722b243 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tmw_info b/Quartus/A2/db/assignment2.tmw_info new file mode 100644 index 0000000..318b33b --- /dev/null +++ b/Quartus/A2/db/assignment2.tmw_info @@ -0,0 +1,7 @@ +start_full_compilation:s:00:01:00 +start_analysis_synthesis:s:00:00:14-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:30-start_full_compilation +start_assembler:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:07-start_full_compilation +start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/Quartus/A2/db/assignment2.vpr.ammdb b/Quartus/A2/db/assignment2.vpr.ammdb index fa8be6a..5483578 100644 Binary files a/Quartus/A2/db/assignment2.vpr.ammdb and b/Quartus/A2/db/assignment2.vpr.ammdb differ diff --git a/Quartus/A2/db/prev_cmp_assignment2.qmsg b/Quartus/A2/db/prev_cmp_assignment2.qmsg index 44c1b34..fa4fb6f 100644 --- a/Quartus/A2/db/prev_cmp_assignment2.qmsg +++ b/Quartus/A2/db/prev_cmp_assignment2.qmsg @@ -1,28 +1,8 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792037018446 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792037018447 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 15 15:03:38 2026 " "Processing started: Thu Oct 15 15:03:38 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792037018447 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037018447 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037018447 ""} -{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792037018752 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037027974 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037027974 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792037028114 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 assignment2.sv(100) " "Verilog HDL assignment warning at assignment2.sv(100): truncated value with size 32 to match size of target (10)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792037028120 "|assignment2"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "flags\[2\] 0 assignment2.sv(55) " "Net \"flags\[2\]\" at assignment2.sv(55) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 55 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792037028123 "|assignment2"} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[15\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[15\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_ANOTHER_DRIVER" "assignment2.sv(105) " "Constant driver at assignment2.sv(105)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 105 0 0 } } } 0 10029 "Constant driver at %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[14\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[14\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[13\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[13\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[12\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[12\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[11\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[11\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[10\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[10\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[9\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[9\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[8\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[8\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[7\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[7\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[6\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[6\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[5\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[5\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[4\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[4\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[3\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[3\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[2\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[2\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[1\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[1\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "PC_Reg_Display\[0\] assignment2.sv(107) " "Can't resolve multiple constant drivers for net \"PC_Reg_Display\[0\]\" at assignment2.sv(107)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 107 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028124 ""} -{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" { } { } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792037028126 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 18 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 18 errors, 2 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792037028180 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 15 15:03:48 2026 " "Processing ended: Thu Oct 15 15:03:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792037028180 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792037028180 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792037028180 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028180 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 20 s 2 s " "Quartus Prime Full Compilation was unsuccessful. 20 errors, 2 warnings" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037028888 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792039139461 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792039139462 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 15 15:38:59 2026 " "Processing started: Thu Oct 15 15:38:59 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792039139462 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792039139462 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792039139462 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792039139787 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "6 control_unit " "Found entity 6: control_unit" { } { { "../../modules/control_unit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792039148776 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792039148776 ""} +{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "width ram.sv(13) " "Verilog HDL error at ram.sv(13): object \"width\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 13 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1792039148778 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 0 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792039148840 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 15 15:39:08 2026 " "Processing ended: Thu Oct 15 15:39:08 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792039148840 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792039148840 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792039148840 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792039148840 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 0 s " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 0 warnings" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792039149490 ""} diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb index 475b3b0..d4b55eb 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb index 7e782ee..4045321 100644 Binary files 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b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb index fc419c2..b02eff0 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi index a1d0bac..90d6fcd 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb index 5b624e0..1aaef6c 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb index 4b3a4b8..43d0c24 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb index aafd113..3154d64 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.kpt b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.kpt index cbdd95c..d5d58dc 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.kpt and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.kpt differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb index 6b5bf26..41380ab 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb differ diff --git a/Quartus/A2/output_files/assignment2.asm.rpt b/Quartus/A2/output_files/assignment2.asm.rpt index df3a6a1..61475b2 100644 --- a/Quartus/A2/output_files/assignment2.asm.rpt +++ b/Quartus/A2/output_files/assignment2.asm.rpt @@ -1,5 +1,5 @@ Assembler report for assignment2 -Tue Oct 13 16:48:13 2026 +Fri Oct 16 09:58:56 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Oct 13 16:48:13 2026 ; +; Assembler Status ; Successful - Fri Oct 16 09:58:56 2026 ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; ; Family ; Cyclone V ; @@ -67,8 +67,8 @@ on the Quartus Prime software download page. +----------------+--------------------------+ ; Option ; Setting ; +----------------+--------------------------+ -; JTAG usercode ; 0x00780D54 ; -; Checksum ; 0x00780D54 ; +; JTAG usercode ; 0x00780AC3 ; +; Checksum ; 0x00780AC3 ; +----------------+--------------------------+ @@ -78,12 +78,12 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 16:48:07 2026 + Info: Processing started: Fri Oct 16 09:58:50 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 516 megabytes - Info: Processing ended: Tue Oct 13 16:48:13 2026 + Info: Peak virtual memory: 520 megabytes + Info: Processing ended: Fri Oct 16 09:58:56 2026 Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A2/output_files/assignment2.done b/Quartus/A2/output_files/assignment2.done index e410369..6a57786 100644 --- a/Quartus/A2/output_files/assignment2.done +++ b/Quartus/A2/output_files/assignment2.done @@ -1 +1 @@ -Tue Oct 13 16:48:22 2026 +Fri Oct 16 09:59:05 2026 diff --git a/Quartus/A2/output_files/assignment2.drc.rpt b/Quartus/A2/output_files/assignment2.drc.rpt new file mode 100644 index 0000000..da2a5d5 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.drc.rpt @@ -0,0 +1,194 @@ +Design Assistant report for assignment2 +Thu Oct 15 15:37:35 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Design Assistant Summary + 3. Design Assistant Settings + 4. Information only Violations + 5. Design Assistant Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-------------------------------------------------------------------------+ +; Design Assistant Summary ; ++-----------------------------------+-------------------------------------+ +; Design Assistant Status ; Analyzed - Thu Oct 15 15:37:35 2026 ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Total Critical Violations ; 0 ; +; Total High Violations ; 0 ; +; Total Medium Violations ; 0 ; +; Total Information only Violations ; 40 ; +; - Rule T102 ; 40 ; ++-----------------------------------+-------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Design Assistant Settings ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ +; Option ; Setting ; To ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ +; Design Assistant mode ; Post-Fitting ; ; +; Threshold value for clock net not mapped to clock spines rule ; 25 ; ; +; Minimum number of clock port feed by gated clocks ; 30 ; ; +; Minimum number of node fan-out ; 30 ; ; +; Maximum number of nodes to report ; 50 ; ; +; Rule C101: Gated clock should be implemented according to the Intel FPGA standard scheme ; On ; ; +; Rule C102: Logic cell should not be used to generate an inverted clock signal ; On ; ; +; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; On ; ; +; Rule C104: Clock signal source should drive only clock input ports ; On ; ; +; Rule C105: Clock signal should be a global signal ; On ; ; +; Rule C106: Clock signal source should not drive registers triggered by different clock edges ; On ; ; +; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ; +; Rule R102: External reset signals should be synchronized using two cascaded registers ; On ; ; +; Rule R103: External reset signal should be correctly synchronized ; On ; ; +; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized ; On ; ; +; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized ; On ; ; +; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ; +; Rule T102: Top nodes with the highest number of fan-outs ; On ; ; +; Rule A101: Design should not contain combinational loops ; On ; ; +; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ; +; Rule A103: Design should not contain delay chains ; On ; ; +; Rule A104: Design should not contain ripple clock structures ; On ; ; +; Rule A105: Pulses should not be implemented asynchronously ; On ; ; +; Rule A106: Multiple pulses should not be generated in design ; On ; ; +; Rule A107: Design should not contain SR latches ; On ; ; +; Rule A108: Design should not contain latches ; On ; ; +; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ; +; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ; +; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source ; On ; ; +; Rule S104: Clock port and any other port of a register should not be driven by the same signal source ; On ; ; +; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ; +; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ; +; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ + + ++------------------------------------------------------------------------------------------+ +; Information only Violations ; ++----------------------------------------------------------+---------------------+---------+ +; Rule name ; Name ; Fan-Out ; ++----------------------------------------------------------+---------------------+---------+ +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[6]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[4]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[7]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[3]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[1]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[2]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[2]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[3]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[4]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[1]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[5]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[0]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[0]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[7]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[0]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[7]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[1]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[2]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[6]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[3]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[4]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[5]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[3] ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; HID_PC[0] ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; HID_Hi_Low[0] ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[4] ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[0]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[7]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[1]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[6]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[2]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[6]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[3]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[2] ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[4]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[1] ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[5]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[5]~output ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[0] ; 1 ; +; Rule T102: Top nodes with the highest number of fan-outs ; clk[0] ; 1 ; ++----------------------------------------------------------+---------------------+---------+ + + ++---------------------------+ +; Design Assistant Messages ; ++---------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Design Assistant + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Thu Oct 15 15:37:34 2026 +Info: Command: quartus_drc assignment2 -c assignment2 +Critical Warning (332012): Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (308044): (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 40 node(s) with highest fan-out. + Info (308011): Node "out_seg_1[6]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Info (308011): Node "out_seg_3[4]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Info (308011): Node "out_seg_0[7]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Info (308011): Node "out_seg_3[3]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Info (308011): Node "out_seg_1[1]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Info (308011): Node "out_seg_1[2]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Info (308011): Node "out_seg_3[2]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Info (308011): Node "out_seg_1[3]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Info (308011): Node "out_seg_1[4]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Info (308011): Node "out_seg_3[1]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Info (308011): Node "out_seg_1[5]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Info (308011): Node "out_seg_1[0]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Info (308011): Node "out_seg_3[0]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Info (308011): Node "out_seg_1[7]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Info (308011): Node "out_seg_2[0]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Info (308011): Node "out_seg_2[7]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Info (308011): Node "out_seg_2[1]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Info (308011): Node "out_seg_2[2]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Info (308011): Node "out_seg_2[6]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Info (308011): Node "out_seg_2[3]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Info (308011): Node "out_seg_2[4]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Info (308011): Node "out_seg_2[5]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Info (308011): Node "HID_Register[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19 + Info (308011): Node "HID_PC[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 20 + Info (308011): Node "HID_Hi_Low[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Info (308011): Node "HID_Register[4]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19 + Info (308011): Node "out_seg_0[0]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Info (308011): Node "out_seg_3[7]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Info (308011): Node "out_seg_0[1]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Info (308011): Node "out_seg_0[6]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated. +Info (308007): Design Assistant information: finished post-fitting analysis of current design -- generated 40 information messages and 0 warning messages +Info: Quartus Prime Design Assistant was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 646 megabytes + Info: Processing ended: Thu Oct 15 15:37:35 2026 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/Quartus/A2/output_files/assignment2.eda.rpt b/Quartus/A2/output_files/assignment2.eda.rpt index b01099f..6b08d43 100644 --- a/Quartus/A2/output_files/assignment2.eda.rpt +++ b/Quartus/A2/output_files/assignment2.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for assignment2 -Tue Oct 13 16:48:22 2026 +Fri Oct 16 09:59:05 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:48:22 2026 ; +; EDA Netlist Writer Status ; Successful - Fri Oct 16 09:59:05 2026 ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; ; Family ; Cyclone V ; @@ -81,12 +81,12 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 16:48:21 2026 + Info: Processing started: Fri Oct 16 09:59:04 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 670 megabytes - Info: Processing ended: Tue Oct 13 16:48:22 2026 + Info: Peak virtual memory: 669 megabytes + Info: Processing ended: Fri Oct 16 09:59:05 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A2/output_files/assignment2.fit.rpt b/Quartus/A2/output_files/assignment2.fit.rpt index 69b0697..95ddb55 100644 --- a/Quartus/A2/output_files/assignment2.fit.rpt +++ b/Quartus/A2/output_files/assignment2.fit.rpt @@ -1,5 +1,5 @@ Fitter report for assignment2 -Tue Oct 13 16:48:05 2026 +Fri Oct 16 09:58:48 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -58,7 +58,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Oct 13 16:48:05 2026 ; +; Fitter Status ; Successful - Fri Oct 16 09:58:48 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; @@ -1190,14 +1190,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ ; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; +-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ -; clk[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; HID_Register[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; HID_Register[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; HID_Register[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; HID_Register[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; HID_Register[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; HID_PC[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; HID_Hi_Low[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; out_seg_0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; out_seg_0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; out_seg_0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; @@ -1230,6 +1223,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; out_seg_3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; out_seg_3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; out_seg_3[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HID_Hi_Low[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; clk[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ @@ -1238,14 +1238,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------+-------------------+---------+ ; Source Pin / Fanout ; Pad To Core Index ; Setting ; +---------------------+-------------------+---------+ -; clk[0] ; ; ; -; HID_Register[0] ; ; ; -; HID_Register[1] ; ; ; -; HID_Register[2] ; ; ; -; HID_Register[3] ; ; ; -; HID_Register[4] ; ; ; ; HID_PC[0] ; ; ; ; HID_Hi_Low[0] ; ; ; +; HID_Register[4] ; ; ; +; HID_Register[2] ; ; ; +; HID_Register[0] ; ; ; +; HID_Register[1] ; ; ; +; HID_Register[3] ; ; ; +; clk[0] ; ; ; +---------------------+-------------------+---------+ @@ -1334,14 +1334,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; Total Inapplicable ; 40 ; 4 ; 4 ; 40 ; 40 ; 0 ; 4 ; 40 ; 40 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 0 ; 0 ; 40 ; ; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; clk[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; HID_Register[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; HID_Register[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; HID_Register[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; HID_Register[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; HID_Register[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; HID_PC[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; HID_Hi_Low[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; out_seg_0[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; out_seg_0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; out_seg_0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; @@ -1374,6 +1367,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; out_seg_3[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; out_seg_3[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; out_seg_3[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Hi_Low[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; clk[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ @@ -1465,9 +1465,9 @@ Info (334004): Delay annotation completed successfully Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 1328 megabytes - Info: Processing ended: Tue Oct 13 16:48:06 2026 - Info: Elapsed time: 00:00:28 + Info: Peak virtual memory: 1336 megabytes + Info: Processing ended: Fri Oct 16 09:58:49 2026 + Info: Elapsed time: 00:00:29 Info: Total CPU time (on all processors): 00:00:39 diff --git a/Quartus/A2/output_files/assignment2.fit.summary b/Quartus/A2/output_files/assignment2.fit.summary index eae105d..5ba69f8 100644 --- a/Quartus/A2/output_files/assignment2.fit.summary +++ b/Quartus/A2/output_files/assignment2.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Oct 13 16:48:05 2026 +Fitter Status : Successful - Fri Oct 16 09:58:48 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : assignment2 Top-level Entity Name : assignment2 diff --git a/Quartus/A2/output_files/assignment2.flow.rpt b/Quartus/A2/output_files/assignment2.flow.rpt index 0828792..3d5d4cc 100644 --- a/Quartus/A2/output_files/assignment2.flow.rpt +++ b/Quartus/A2/output_files/assignment2.flow.rpt @@ -1,5 +1,5 @@ Flow report for assignment2 -Thu Oct 15 15:04:20 2026 +Fri Oct 16 09:59:05 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,24 +38,29 @@ on the Quartus Prime software download page. -+-------------------------------------------------------------------------------+ -; Flow Summary ; -+-----------------------------+-------------------------------------------------+ -; Flow Status ; Flow Failed - Thu Oct 15 15:04:20 2026 ; -; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; -; Revision Name ; assignment2 ; -; Top-level Entity Name ; assignment2 ; -; Family ; Cyclone V ; -; Device ; 5CGXFC5C6F27C7 ; -; Timing Models ; Final ; -; Logic utilization (in ALMs) ; N/A until Partition Merge ; -; Total registers ; N/A until Partition Merge ; -; Total pins ; N/A until Partition Merge ; -; Total virtual pins ; N/A until Partition Merge ; -; Total block memory bits ; N/A until Partition Merge ; -; Total PLLs ; N/A until Partition Merge ; -; Total DLLs ; N/A until Partition Merge ; -+-----------------------------+-------------------------------------------------+ ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Fri Oct 16 09:59:05 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ; +; Total registers ; 0 ; +; Total pins ; 40 / 364 ( 11 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; +; Total DSP Blocks ; 0 / 150 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ; +; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ; +; Total PLLs ; 0 / 12 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+-------------------------------------------------+ +-----------------------------------------+ @@ -63,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 10/15/2026 15:04:10 ; +; Start date & time ; 10/16/2026 09:58:06 ; ; Main task ; Compilation ; ; Revision Name ; assignment2 ; +-------------------+---------------------+ @@ -74,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 268883478169649.179203705005251 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 231344018423319.179210508627966 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -98,8 +103,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 412 MB ; 00:00:24 ; -; Total ; 00:00:10 ; -- ; -- ; 00:00:24 ; +; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 427 MB ; 00:00:26 ; +; Fitter ; 00:00:28 ; 1.0 ; 1336 MB ; 00:00:38 ; +; Assembler ; 00:00:06 ; 1.0 ; 520 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:05 ; 1.0 ; 765 MB ; 00:00:05 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 669 MB ; 00:00:01 ; +; Total ; 00:00:52 ; -- ; -- ; 00:01:15 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ @@ -109,6 +118,10 @@ on the Quartus Prime software download page. ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +----------------------+---------------------+------------+------------+----------------+ ; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Fitter ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Assembler ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Timing Analyzer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; EDA Netlist Writer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +----------------------+---------------------+------------+------------+----------------+ @@ -116,6 +129,10 @@ on the Quartus Prime software download page. ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 +quartus_fit --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 +quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 +quartus_sta assignment2 -c assignment2 +quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 diff --git a/Quartus/A2/output_files/assignment2.map.rpt b/Quartus/A2/output_files/assignment2.map.rpt index 81dba9a..ff93163 100644 --- a/Quartus/A2/output_files/assignment2.map.rpt +++ b/Quartus/A2/output_files/assignment2.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for assignment2 -Thu Oct 15 15:04:20 2026 +Fri Oct 16 09:58:19 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -10,7 +10,35 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation - 5. Analysis & Synthesis Messages + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Registers Removed During Synthesis + 9. Removed Registers Triggering Further Register Optimizations + 10. General Register Statistics + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Parameter Settings for User Entity Instance: Top-level Entity: |assignment2 + 13. Parameter Settings for User Entity Instance: instruction_counter:PC + 14. Parameter Settings for User Entity Instance: rom:ROM + 15. Parameter Settings for User Entity Instance: ram:RAM + 16. Parameter Settings for User Entity Instance: register_file:REGS + 17. Parameter Settings for User Entity Instance: sign_extender:SIGNEXT + 18. Parameter Settings for User Entity Instance: alu:ALU + 19. Parameter Settings for User Entity Instance: alu:ALU|asu:adder_unit + 20. Parameter Settings for User Entity Instance: alu:ALU|lu:logic_unit + 21. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit3" + 22. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit2" + 23. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit1" + 24. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit0" + 25. Port Connectivity Checks: "alu:ALU" + 26. Port Connectivity Checks: "sign_extender:SIGNEXT" + 27. Port Connectivity Checks: "control_unit:CONTROL_UNIT|instruction_classifier:CLASSIFIER" + 28. Port Connectivity Checks: "control_unit:CONTROL_UNIT" + 29. Port Connectivity Checks: "ram:RAM" + 30. Port Connectivity Checks: "instruction_counter:PC" + 31. Post-Synthesis Netlist Statistics for Top Partition + 32. Elapsed Time Per Partition + 33. Analysis & Synthesis Messages @@ -34,22 +62,27 @@ on the Quartus Prime software download page. -+-------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Failed - Thu Oct 15 15:04:20 2026 ; -; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; -; Revision Name ; assignment2 ; -; Top-level Entity Name ; assignment2 ; -; Family ; Cyclone V ; -; Logic utilization (in ALMs) ; N/A until Partition Merge ; -; Total registers ; N/A until Partition Merge ; -; Total pins ; N/A until Partition Merge ; -; Total virtual pins ; N/A until Partition Merge ; -; Total block memory bits ; N/A until Partition Merge ; -; Total PLLs ; N/A until Partition Merge ; -; Total DLLs ; N/A until Partition Merge ; -+-----------------------------+-------------------------------------------------+ ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++---------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Fri Oct 16 09:58:19 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 0 ; +; Total pins ; 40 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+-------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------+ @@ -156,13 +189,5848 @@ on the Quartus Prime software download page. +----------------------------+-------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------------------------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------------------------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------+---------+ +; ../../modules/assignment2.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv ; ; +; ../../modules/rom.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv ; ; +; ../../modules/ram.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv ; ; +; ../../modules/register_file.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv ; ; +; ../../modules/instruction_counter.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv ; ; +; ../../modules/instruction_classifier.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv ; ; +; ../../modules/control_unit.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv ; ; +; ../../modules/asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ; +; ../../modules/lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv ; ; +; ../../modules/alu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ; +; ../../modules/shifter.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv ; ; +; ../../modules/sign_extender.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv ; ; +; ../../modules/seven_seg.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv ; ; +; ../../modules/seven_seg_4digit.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv ; ; +; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; yes ; Auto-Found File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; ; ++----------------------------------------------------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------+---------+ + + ++---------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-----------+ +; Resource ; Usage ; ++---------------------------------------------+-----------+ +; Estimate of Logic utilization (ALMs needed) ; 0 ; +; ; ; +; Combinational ALUT usage for logic ; 0 ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 0 ; +; -- 5 input functions ; 0 ; +; -- 4 input functions ; 0 ; +; -- <=3 input functions ; 0 ; +; ; ; +; Dedicated logic registers ; 0 ; +; ; ; +; I/O pins ; 40 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; HID_PC[0] ; +; Maximum fan-out ; 1 ; +; Total fan-out ; 40 ; +; Average fan-out ; 0.50 ; ++---------------------------------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ +; |assignment2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 40 ; 0 ; |assignment2 ; assignment2 ; work ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++------------------------------------------+---------------------------------------------+ +; Register name ; Reason for Removal ; ++------------------------------------------+---------------------------------------------+ +; instruction_counter:PC|pc[0,1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[0][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][3] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][19] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][2] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][18] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][17] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][16] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][7] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][23] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][6] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][22] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][5] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][21] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][4] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][20] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][11] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][27] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][10] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][26] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][9] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][25] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][8] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][24] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][15] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][31] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][14] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][30] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][13] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][29] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][12] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[4][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[8][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[9][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[10][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[12][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[13][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[14][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[16][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[17][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[18][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[19][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[20][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[21][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[22][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[23][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[24][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[25][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[26][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[27][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[28][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[29][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[30][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[31][28] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[0][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[16][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[17][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[18][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[19][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[20][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[21][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[22][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[23][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[24][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[25][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[26][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[27][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[28][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[29][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[30][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[31][1] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[0][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[16][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[17][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[18][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[19][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[20][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[21][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[22][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[23][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[24][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[25][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[26][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[27][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[28][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[29][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[30][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[31][0] ; Stuck at GND due to stuck port clock_enable ; +; register_file:REGS|regs[1][1] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][1] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][1] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][1] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][1] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][1] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][1] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][1] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[1][0] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[2][0] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[3][0] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[15][0] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[5][0] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[6][0] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[7][0] ; Stuck at GND due to stuck port data_in ; +; register_file:REGS|regs[11][0] ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~0 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~6 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~8 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~10 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~12 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~14 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~16 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~18 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~20 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~22 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~24 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~26 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~28 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~30 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~32 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~34 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~36 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~38 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~40 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~42 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~44 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~46 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~48 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~50 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~52 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~54 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~56 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~58 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~60 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~62 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~64 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~66 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~68 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~70 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~72 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~74 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~76 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~78 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~80 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~82 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~84 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~86 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~88 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~90 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~92 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~94 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~96 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~98 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~100 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~102 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~104 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~106 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~108 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~110 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~112 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~114 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~116 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~118 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~120 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~122 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~124 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~126 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~128 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~130 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~132 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~134 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~136 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~138 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~140 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~142 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~144 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~146 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~148 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~150 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~152 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~154 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~156 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~158 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~160 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~162 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~164 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~166 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~168 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~170 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~172 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~174 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~176 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~178 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~180 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~182 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~184 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~186 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~188 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~190 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~192 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~194 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~196 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~198 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~200 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~202 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~204 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~206 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~208 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~210 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~212 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~214 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~216 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~218 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~220 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~222 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~224 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~226 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~228 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~230 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~232 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~234 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~236 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~238 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~240 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~242 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~244 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~246 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~248 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~250 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~252 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~254 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~256 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~258 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~260 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~262 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~264 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~266 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~268 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~270 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~272 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~274 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~276 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~278 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~280 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~282 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~284 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~286 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~288 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~290 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~292 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~294 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~296 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~298 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~300 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~302 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~304 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~306 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~308 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~310 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~312 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~314 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~316 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~318 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~320 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~322 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~324 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~326 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~328 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~330 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~332 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~334 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~336 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~338 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~340 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~342 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~344 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~346 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~348 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~350 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~352 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~354 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~356 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~358 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~360 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~362 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~364 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~366 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~368 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~370 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~372 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~374 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~376 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~378 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~380 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~382 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~384 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~386 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~388 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~390 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~392 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~394 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~396 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~398 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~400 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~402 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~404 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~406 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~408 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~410 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~412 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~414 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~416 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~418 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~420 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~422 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~424 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~426 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~428 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~430 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~432 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~434 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~436 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~438 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~440 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~442 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~444 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~446 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~448 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~450 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~452 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~454 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~456 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~458 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~460 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~462 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~464 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~466 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~468 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~470 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~472 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~474 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~476 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~478 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~480 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~482 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~484 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~486 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~488 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~490 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~492 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~494 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~496 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~498 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~500 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~502 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~504 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~506 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~508 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~510 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~512 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~514 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~516 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~518 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~520 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~522 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~524 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~526 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~528 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~530 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~532 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~534 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~536 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~538 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~540 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~542 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~544 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~546 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~548 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~550 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~552 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~554 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~556 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~558 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~560 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~562 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~564 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~566 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~568 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~570 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~572 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~574 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~576 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~578 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~580 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~582 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~584 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~586 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~588 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~590 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~592 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~594 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~596 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~598 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~600 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~602 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~604 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~606 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~608 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~610 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~612 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~614 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~616 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~618 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~620 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~622 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~624 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~626 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~628 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~630 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~632 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~634 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~636 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~638 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~640 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~642 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~644 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~646 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~648 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~650 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~652 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~654 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~656 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~658 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~660 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~662 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~664 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~666 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~668 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~670 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~672 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~674 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~676 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~678 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~680 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~682 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~684 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~686 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~688 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~690 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~692 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~694 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~696 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~698 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~700 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~702 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~704 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~706 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~708 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~710 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~712 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~714 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~716 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~718 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~720 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~722 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~724 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~726 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~728 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~730 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~732 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~734 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~736 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~738 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~740 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~742 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~744 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~746 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~748 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~750 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~752 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~754 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~756 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~758 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~760 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~762 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~764 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~766 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~768 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~770 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~772 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~774 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~776 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~778 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~780 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~782 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~784 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~786 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~788 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~790 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~792 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~794 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~796 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~798 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~800 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~802 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~804 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~806 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~808 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~810 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~812 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~814 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~816 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~818 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~820 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~822 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~824 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~826 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~828 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~830 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~832 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~834 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~836 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~838 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~840 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~842 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~844 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~846 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~848 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~850 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~852 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~854 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~856 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~858 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~860 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~862 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~864 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~866 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~868 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~870 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~872 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~874 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~876 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~878 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~880 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~882 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~884 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~886 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~888 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~890 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~892 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~894 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~896 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~898 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~900 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~902 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~904 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~906 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~908 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~910 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~912 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~914 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~916 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~918 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~920 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~922 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~924 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~926 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~928 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~930 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~932 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~934 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~936 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~938 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~940 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~942 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~944 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~946 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~948 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~950 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~952 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~954 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~956 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~958 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~960 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~962 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~964 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~966 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~968 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~970 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~972 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~974 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~976 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~978 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~980 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~982 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~984 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~986 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~988 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~990 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~992 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~994 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~996 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~998 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1000 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1002 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1004 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1006 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1008 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1010 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1012 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1014 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1016 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1018 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1020 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1022 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1024 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1026 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1028 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1030 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1032 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1034 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1036 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1038 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1040 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1042 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1044 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1046 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1048 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1050 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1052 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1054 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1056 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1058 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1060 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1062 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1064 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1066 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1068 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1070 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1072 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1074 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1076 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1078 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1080 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1082 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1084 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1086 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1088 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1090 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1092 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1094 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1096 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1098 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1100 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1102 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1104 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1106 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1108 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1110 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1112 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1114 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1116 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1118 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1120 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1122 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1124 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1126 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1128 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1130 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1132 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1134 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1136 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1138 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1140 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1142 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1144 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1146 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1148 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1150 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1152 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1154 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1156 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1158 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1160 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1162 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1164 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1166 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1168 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1170 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1172 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1174 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1176 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1178 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1180 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1182 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1184 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1186 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1188 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1190 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1192 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1194 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1196 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1198 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1200 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1202 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1204 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1206 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1208 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1210 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1212 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1214 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1216 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1218 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1220 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1222 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1224 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1226 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1228 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1230 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1232 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1234 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1236 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1238 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1240 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1242 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1244 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1246 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1248 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1250 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1252 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1254 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1256 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1258 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1260 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1262 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1264 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1266 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1268 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1270 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1272 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1274 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1276 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1278 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1280 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1282 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1284 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1286 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1288 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1290 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1292 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1294 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1296 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1298 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1300 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1302 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1304 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1306 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1308 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1310 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1312 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1314 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1316 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1318 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1320 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1322 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1324 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1326 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1328 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1330 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1332 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1334 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1336 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1338 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1340 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1342 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1344 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1346 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1348 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1350 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1352 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1354 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1356 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1358 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1360 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1362 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1364 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1366 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1368 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1370 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1372 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1374 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1376 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1378 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1380 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1382 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1384 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1386 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1388 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1390 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1392 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1394 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1396 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1398 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1400 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1402 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1404 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1406 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1408 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1410 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1412 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1414 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1416 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1418 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1420 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1422 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1424 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1426 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1428 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1430 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1432 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1434 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1436 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1438 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1440 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1442 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1444 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1446 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1448 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1450 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1452 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1454 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1456 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1458 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1460 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1462 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1464 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1466 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1468 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1470 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1472 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1474 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1476 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1478 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1480 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1482 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1484 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1486 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1488 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1490 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1492 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1494 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1496 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1498 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1500 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1502 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1504 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1506 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1508 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1510 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1512 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1514 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1516 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1518 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1520 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1522 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1524 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1526 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1528 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1530 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1532 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1534 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1536 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1538 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1540 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1542 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1544 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1546 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1548 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1550 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1552 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1554 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1556 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1558 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1560 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1562 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1564 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1566 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1568 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1570 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1572 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1574 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1576 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1578 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1580 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1582 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1584 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1586 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1588 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1590 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1592 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1594 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1596 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1598 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1600 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1602 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1604 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1606 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1608 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1610 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1612 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1614 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1616 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1618 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1620 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1622 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1624 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1626 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1628 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1630 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1632 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1634 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1636 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1638 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1640 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1642 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1644 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1646 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1648 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1650 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1652 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1654 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1656 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1658 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1660 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1662 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1664 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1666 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1668 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1670 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1672 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1674 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1676 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1678 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1680 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1682 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1684 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1686 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1688 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1690 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1692 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1694 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1696 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1698 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1700 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1702 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1704 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1706 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1708 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1710 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1712 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1714 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1716 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1718 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1720 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1722 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1724 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1726 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1728 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1730 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1732 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1734 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1736 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1738 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1740 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1742 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1744 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1746 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1748 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1750 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1752 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1754 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1756 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1758 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1760 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1762 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1764 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1766 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1768 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1770 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1772 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1774 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1776 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1778 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1780 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1782 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1784 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1786 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1788 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1790 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1792 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1794 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1796 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1798 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1800 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1802 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1804 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1806 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1808 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1810 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1812 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1814 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1816 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1818 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1820 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1822 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1824 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1826 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1828 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1830 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1832 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1834 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1836 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1838 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1840 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1842 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1844 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1846 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1848 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1850 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1852 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1854 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1856 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1858 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1860 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1862 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1864 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1866 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1868 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1870 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1872 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1874 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1876 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1878 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1880 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1882 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1884 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1886 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1888 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1890 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1892 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1894 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1896 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1898 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1900 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1902 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1904 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1906 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1908 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1910 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1912 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1914 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1916 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1918 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1920 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1922 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1924 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1926 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1928 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1930 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1932 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1934 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1936 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1938 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1940 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1942 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1944 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1946 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1948 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1950 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1952 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1954 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1956 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1958 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1960 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1962 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1964 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1966 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1968 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1970 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1972 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1974 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1976 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1978 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1980 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1982 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1984 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1986 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1988 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1990 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1992 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1994 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1996 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1998 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2000 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2002 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2004 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2006 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2008 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2010 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2012 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2014 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2016 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2018 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2020 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2022 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2024 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2026 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2028 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2030 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2032 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2034 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2036 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2038 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2040 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2042 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2044 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2046 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2048 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2050 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2052 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2054 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2056 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2058 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2060 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2062 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2064 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2066 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2068 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2070 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2072 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2074 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2076 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2078 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2080 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2082 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2084 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2086 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2088 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2090 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2092 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2094 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2096 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2098 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2100 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2102 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2104 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2106 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2108 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2110 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2112 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2114 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2116 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2118 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2120 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2122 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2124 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2126 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2128 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2130 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2132 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2134 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2136 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2138 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2140 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2142 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2144 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2146 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2148 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2150 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2152 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2154 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2156 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2158 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2160 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2162 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2164 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2166 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2168 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2170 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2172 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2174 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2176 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2178 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2180 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2182 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2184 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2186 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2188 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2190 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2192 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2194 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2196 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2198 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2200 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2202 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2204 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2206 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2208 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2210 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2212 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2214 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2216 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2218 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2220 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2222 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2224 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2226 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2228 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2230 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2232 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2234 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2236 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2238 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2240 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2242 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2244 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2246 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2248 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2250 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2252 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2254 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2256 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2258 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2260 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2262 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2264 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2266 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2268 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2270 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2272 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2274 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2276 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2278 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2280 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2282 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2284 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2286 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2288 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2290 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2292 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2294 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2296 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2298 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2300 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2302 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2304 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2306 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2308 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2310 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2312 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2314 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2316 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2318 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2320 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2322 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2324 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2326 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2328 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2330 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2332 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2334 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2336 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2338 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2340 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2342 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2344 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2346 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2348 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2350 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2352 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2354 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2356 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2358 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2360 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2362 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2364 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2366 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2368 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2370 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2372 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2374 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2376 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2378 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2380 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2382 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2384 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2386 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2388 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2390 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2392 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2394 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2396 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2398 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2400 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2402 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2404 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2406 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2408 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2410 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2412 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2414 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2416 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2418 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2420 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2422 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2424 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2426 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2428 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2430 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2432 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2434 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2436 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2438 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2440 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2442 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2444 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2446 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2448 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2450 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2452 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2454 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2456 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2458 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2460 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2462 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2464 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2466 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2468 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2470 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2472 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2474 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2476 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2478 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2480 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2482 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2484 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2486 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2488 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2490 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2492 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2494 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2496 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2498 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2500 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2502 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2504 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2506 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2508 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2510 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2512 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2514 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2516 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2518 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2520 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2522 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2524 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2526 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2528 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2530 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2532 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2534 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2536 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2538 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2540 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2542 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2544 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2546 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2548 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2550 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2552 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2554 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2556 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2558 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2560 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2562 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2564 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2566 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2568 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2570 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2572 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2574 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2576 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2578 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2580 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2582 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2584 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2586 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2588 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2590 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2592 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2594 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2596 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2598 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2600 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2602 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2604 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2606 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2608 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2610 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2612 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2614 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2616 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2618 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2620 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2622 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2624 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2626 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2628 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2630 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2632 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2634 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2636 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2638 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2640 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2642 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2644 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2646 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2648 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2650 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2652 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2654 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2656 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2658 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2660 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2662 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2664 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2666 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2668 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2670 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2672 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2674 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2676 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2678 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2680 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2682 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2684 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2686 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2688 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2690 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2692 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2694 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2696 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2698 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2700 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2702 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2704 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2706 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2708 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2710 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2712 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2714 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2716 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2718 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2720 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2722 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2724 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2726 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2728 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2730 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2732 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2734 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2736 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2738 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2740 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2742 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2744 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2746 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2748 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2750 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2752 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2754 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2756 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2758 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2760 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2762 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2764 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2766 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2768 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2770 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2772 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2774 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2776 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2778 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2780 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2782 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2784 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2786 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2788 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2790 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2792 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2794 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2796 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2798 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2800 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2802 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2804 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2806 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2808 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2810 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2812 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2814 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2816 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2818 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2820 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2822 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2824 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2826 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2828 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2830 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2832 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2834 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2836 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2838 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2840 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2842 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2844 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2846 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2848 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2850 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2852 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2854 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2856 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2858 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2860 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2862 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2864 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2866 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2868 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2870 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2872 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2874 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2876 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2878 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2880 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2882 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2884 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2886 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2888 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2890 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2892 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2894 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2896 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2898 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2900 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2902 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2904 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2906 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2908 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2910 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2912 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2914 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2916 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2918 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2920 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2922 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2924 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2926 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2928 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2930 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2932 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2934 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2936 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2938 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2940 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2942 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2944 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2946 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2948 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2950 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2952 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2954 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2956 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2958 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2960 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2962 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2964 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2966 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2968 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2970 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2972 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2974 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2976 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2978 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2980 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2982 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2984 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2986 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2988 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2990 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2992 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2994 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2996 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2998 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3000 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3002 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3004 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3006 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3008 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3010 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3012 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3014 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3016 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3018 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3020 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3022 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3024 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3026 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3028 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3030 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3032 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3034 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3036 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3038 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3040 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3042 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3044 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3046 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3048 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3050 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3052 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3054 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3056 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3058 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3060 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3062 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3064 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3066 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3068 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3070 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3072 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3074 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3076 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3078 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3080 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3082 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3084 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3086 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3088 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3090 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3092 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3094 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3096 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3098 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3100 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3102 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3104 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3106 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3108 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3110 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3112 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3114 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3116 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3118 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3120 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3122 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3124 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3126 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3128 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3130 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3132 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3134 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3136 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3138 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3140 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3142 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3144 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3146 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3148 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3150 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3152 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3154 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3156 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3158 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3160 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3162 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3164 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3166 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3168 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3170 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3172 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3174 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3176 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3178 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3180 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3182 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3184 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3186 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3188 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3190 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3192 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3194 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3196 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3198 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3200 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3202 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3204 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3206 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3208 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3210 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3212 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3214 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3216 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3218 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3220 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3222 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3224 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3226 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3228 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3230 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3232 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3234 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3236 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3238 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3240 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3242 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3244 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3246 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3248 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3250 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3252 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3254 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3256 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3258 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3260 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3262 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3264 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3266 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3268 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3270 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3272 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3274 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3276 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3278 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3280 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3282 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3284 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3286 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3288 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3290 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3292 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3294 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3296 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3298 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3300 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3302 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3304 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3306 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3308 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3310 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3312 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3314 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3316 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3318 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3320 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3322 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3324 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3326 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3328 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3330 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3332 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3334 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3336 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3338 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3340 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3342 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3344 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3346 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3348 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3350 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3352 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3354 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3356 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3358 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3360 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3362 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3364 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3366 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3368 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3370 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3372 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3374 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3376 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3378 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3380 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3382 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3384 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3386 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3388 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3390 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3392 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3394 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3396 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3398 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3400 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3402 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3404 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3406 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3408 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3410 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3412 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3414 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3416 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3418 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3420 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3422 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3424 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3426 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3428 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3430 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3432 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3434 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3436 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3438 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3440 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3442 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3444 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3446 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3448 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3450 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3452 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3454 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3456 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3458 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3460 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3462 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3464 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3466 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3468 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3470 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3472 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3474 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3476 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3478 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3480 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3482 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3484 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3486 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3488 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3490 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3492 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3494 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3496 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3498 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3500 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3502 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3504 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3506 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3508 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3510 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3512 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3514 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3516 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3518 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3520 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3522 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3524 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3526 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3528 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3530 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3532 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3534 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3536 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3538 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3540 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3542 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3544 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3546 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3548 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3550 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3552 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3554 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3556 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3558 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3560 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3562 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3564 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3566 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3568 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3570 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3572 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3574 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3576 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3578 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3580 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3582 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3584 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3586 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3588 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3590 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3592 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3594 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3596 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3598 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3600 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3602 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3604 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3606 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3608 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3610 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3612 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3614 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3616 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3618 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3620 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3622 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3624 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3626 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3628 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3630 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3632 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3634 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3636 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3638 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3640 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3642 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3644 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3646 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3648 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3650 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3652 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3654 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3656 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3658 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3660 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3662 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3664 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3666 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3668 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3670 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3672 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3674 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3676 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3678 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3680 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3682 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3684 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3686 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3688 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3690 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3692 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3694 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3696 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3698 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3700 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3702 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3704 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3706 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3708 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3710 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3712 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3714 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3716 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3718 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3720 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3722 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3724 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3726 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3728 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3730 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3732 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3734 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3736 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3738 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3740 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3742 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3744 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3746 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3748 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3750 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3752 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3754 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3756 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3758 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3760 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3762 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3764 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3766 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3768 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3770 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3772 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3774 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3776 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3778 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3780 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3782 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3784 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3786 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3788 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3790 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3792 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3794 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3796 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3798 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3800 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3802 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3804 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3806 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3808 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3810 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3812 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3814 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3816 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3818 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3820 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3822 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3824 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3826 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3828 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3830 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3832 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3834 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3836 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3838 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3840 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3842 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3844 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3846 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3848 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3850 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3852 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3854 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3856 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3858 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3860 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3862 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3864 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3866 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3868 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3870 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3872 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3874 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3876 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3878 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3880 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3882 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3884 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3886 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3888 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3890 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3892 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3894 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3896 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3898 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3900 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3902 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3904 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3906 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3908 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3910 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3912 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3914 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3916 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3918 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3920 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3922 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3924 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3926 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3928 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3930 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3932 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3934 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3936 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3938 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3940 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3942 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3944 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3946 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3948 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3950 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3952 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3954 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3956 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3958 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3960 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3962 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3964 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3966 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3968 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3970 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3972 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3974 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3976 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3978 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3980 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3982 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3984 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3986 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3988 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3990 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3992 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3994 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3996 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3998 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4000 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4002 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4004 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4006 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4008 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4010 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4012 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4014 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4016 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4018 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4020 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4022 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4024 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4026 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4028 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4030 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4032 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4034 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4036 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4038 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4040 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4042 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4044 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4046 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4048 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4050 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4052 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4054 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4056 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4058 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4060 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4062 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4064 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4066 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4068 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4070 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4072 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4074 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4076 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4078 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4080 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4082 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4084 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4086 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4088 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4090 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4092 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~4094 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~5 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~7 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~9 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~11 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~13 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~15 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~17 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~19 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~21 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~23 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~25 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~27 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~29 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~31 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~33 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~35 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~37 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~39 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~41 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~43 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~45 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~47 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~49 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~51 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~53 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~55 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~57 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~59 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~61 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~63 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~65 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~67 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~69 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~71 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~73 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~75 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~77 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~79 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~81 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~83 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~85 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~87 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~89 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~91 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~93 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~95 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~97 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~99 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~101 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~103 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~105 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~107 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~109 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~111 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~113 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~115 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~117 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~119 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~121 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~123 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~125 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~127 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~129 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~131 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~133 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~135 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~137 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~139 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~141 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~143 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~145 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~147 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~149 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~151 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~153 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~155 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~157 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~159 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~161 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~163 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~165 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~167 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~169 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~171 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~173 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~175 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~177 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~179 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~181 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~183 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~185 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~187 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~189 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~191 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~193 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~195 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~197 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~199 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~201 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~203 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~205 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~207 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~209 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~211 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~213 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~215 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~217 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~219 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~221 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~223 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~225 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~227 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~229 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~231 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~233 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~235 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~237 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~239 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~241 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~243 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~245 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~247 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~249 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~251 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~253 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~255 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~257 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~259 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~261 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~263 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~265 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~267 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~269 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~271 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~273 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~275 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~277 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~279 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~281 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~283 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~285 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~287 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~289 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~291 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~293 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~295 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~297 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~299 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~301 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~303 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~305 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~307 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~309 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~311 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~313 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~315 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~317 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~319 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~321 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~323 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~325 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~327 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~329 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~331 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~333 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~335 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~337 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~339 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~341 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~343 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~345 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~347 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~349 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~351 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~353 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~355 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~357 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~359 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~361 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~363 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~365 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~367 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~369 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~371 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~373 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~375 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~377 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~379 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~381 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~383 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~385 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~387 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~389 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~391 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~393 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~395 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~397 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~399 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~401 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~403 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~405 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~407 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~409 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~411 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~413 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~415 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~417 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~419 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~421 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~423 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~425 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~427 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~429 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~431 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~433 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~435 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~437 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~439 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~441 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~443 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~445 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~447 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~449 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~451 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~453 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~455 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~457 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~459 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~461 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~463 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~465 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~467 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~469 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~471 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~473 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~475 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~477 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~479 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~481 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~483 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~485 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~487 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~489 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~491 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~493 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~495 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~497 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~499 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~501 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~503 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~505 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~507 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~509 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~511 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~513 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~515 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~517 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~519 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~521 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~523 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~525 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~527 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~529 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~531 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~533 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~535 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~537 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~539 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~541 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~543 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~545 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~547 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~549 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~551 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~553 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~555 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~557 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~559 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~561 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~563 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~565 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~567 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~569 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~571 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~573 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~575 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~577 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~579 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~581 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~583 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~585 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~587 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~589 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~591 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~593 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~595 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~597 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~599 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~601 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~603 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~605 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~607 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~609 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~611 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~613 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~615 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~617 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~619 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~621 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~623 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~625 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~627 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~629 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~631 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~633 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~635 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~637 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~639 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~641 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~643 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~645 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~647 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~649 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~651 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~653 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~655 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~657 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~659 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~661 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~663 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~665 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~667 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~669 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~671 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~673 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~675 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~677 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~679 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~681 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~683 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~685 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~687 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~689 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~691 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~693 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~695 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~697 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~699 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~701 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~703 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~705 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~707 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~709 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~711 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~713 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~715 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~717 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~719 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~721 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~723 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~725 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~727 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~729 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~731 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~733 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~735 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~737 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~739 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~741 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~743 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~745 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~747 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~749 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~751 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~753 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~755 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~757 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~759 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~761 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~763 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~765 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~767 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~769 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~771 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~773 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~775 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~777 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~779 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~781 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~783 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~785 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~787 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~789 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~791 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~793 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~795 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~797 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~799 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~801 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~803 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~805 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~807 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~809 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~811 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~813 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~815 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~817 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~819 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~821 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~823 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~825 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~827 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~829 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~831 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~833 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~835 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~837 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~839 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~841 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~843 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~845 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~847 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~849 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~851 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~853 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~855 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~857 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~859 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~861 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~863 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~865 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~867 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~869 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~871 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~873 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~875 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~877 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~879 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~881 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~883 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~885 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~887 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~889 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~891 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~893 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~895 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~897 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~899 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~901 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~903 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~905 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~907 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~909 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~911 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~913 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~915 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~917 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~919 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~921 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~923 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~925 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~927 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~929 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~931 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~933 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~935 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~937 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~939 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~941 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~943 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~945 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~947 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~949 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~951 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~953 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~955 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~957 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~959 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~961 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~963 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~965 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~967 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~969 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~971 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~973 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~975 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~977 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~979 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~981 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~983 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~985 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~987 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~989 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~991 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~993 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~995 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~997 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~999 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1001 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1003 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1005 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1007 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1009 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1011 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1013 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1015 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1017 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1019 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1021 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1023 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1025 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1027 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1029 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1031 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1033 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1035 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1037 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1039 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1041 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1043 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1045 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1047 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1049 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1051 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1053 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1055 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1057 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1059 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1061 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1063 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1065 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1067 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1069 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1071 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1073 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1075 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1077 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1079 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1081 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1083 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1085 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1087 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1089 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1091 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1093 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1095 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1097 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1099 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1101 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1103 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1105 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1107 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1109 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1111 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1113 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1115 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1117 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1119 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1121 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1123 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1125 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1127 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1129 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1131 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1133 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1135 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1137 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1139 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1141 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1143 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1145 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1147 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1149 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1151 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1153 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1155 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1157 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1159 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1161 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1163 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1165 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1167 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1169 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1171 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1173 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1175 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1177 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1179 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1181 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1183 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1185 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1187 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1189 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1191 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1193 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1195 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1197 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1199 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1201 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1203 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1205 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1207 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1209 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1211 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1213 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1215 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1217 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1219 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1221 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1223 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1225 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1227 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1229 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1231 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1233 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1235 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1237 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1239 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1241 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1243 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1245 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1247 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1249 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1251 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1253 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1255 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1257 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1259 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1261 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1263 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1265 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1267 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1269 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1271 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1273 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1275 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1277 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1279 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1281 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1283 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1285 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1287 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1289 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1291 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1293 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1295 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1297 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1299 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1301 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1303 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1305 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1307 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1309 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1311 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1313 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1315 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1317 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1319 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1321 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1323 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1325 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1327 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1329 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1331 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1333 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1335 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1337 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1339 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1341 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1343 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1345 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1347 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1349 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1351 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1353 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1355 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1357 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1359 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1361 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1363 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1365 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1367 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1369 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1371 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1373 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1375 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1377 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1379 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1381 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1383 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1385 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1387 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1389 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1391 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1393 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1395 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1397 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1399 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1401 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1403 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1405 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1407 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1409 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1411 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1413 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1415 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1417 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1419 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1421 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1423 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1425 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1427 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1429 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1431 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1433 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1435 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1437 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1439 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1441 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1443 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1445 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1447 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1449 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1451 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1453 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1455 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1457 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1459 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1461 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1463 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1465 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1467 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1469 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1471 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1473 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1475 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1477 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1479 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1481 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1483 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1485 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1487 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1489 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1491 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1493 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1495 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1497 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1499 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1501 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1503 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1505 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1507 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1509 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1511 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1513 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1515 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1517 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1519 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1521 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1523 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1525 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1527 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1529 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1531 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1533 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1535 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1537 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1539 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1541 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1543 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1545 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1547 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1549 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1551 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1553 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1555 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1557 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1559 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1561 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1563 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1565 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1567 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1569 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1571 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1573 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1575 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1577 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1579 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1581 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1583 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1585 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1587 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1589 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1591 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1593 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1595 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1597 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1599 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1601 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1603 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1605 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1607 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1609 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1611 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1613 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1615 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1617 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1619 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1621 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1623 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1625 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1627 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1629 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1631 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1633 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1635 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1637 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1639 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1641 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1643 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1645 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1647 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1649 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1651 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1653 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1655 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1657 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1659 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1661 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1663 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1665 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1667 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1669 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1671 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1673 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1675 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1677 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1679 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1681 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1683 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1685 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1687 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1689 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1691 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1693 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1695 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1697 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1699 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1701 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1703 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1705 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1707 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1709 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1711 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1713 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1715 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1717 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1719 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1721 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1723 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1725 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1727 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1729 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1731 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1733 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1735 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1737 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1739 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1741 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1743 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1745 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1747 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1749 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1751 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1753 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1755 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1757 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1759 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1761 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1763 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1765 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1767 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1769 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1771 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1773 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1775 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1777 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1779 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1781 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1783 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1785 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1787 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1789 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1791 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1793 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1795 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1797 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1799 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1801 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1803 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1805 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1807 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1809 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1811 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1813 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1815 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1817 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1819 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1821 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1823 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1825 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1827 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1829 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1831 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1833 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1835 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1837 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1839 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1841 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1843 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1845 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1847 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1849 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1851 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1853 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1855 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1857 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1859 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1861 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1863 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1865 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1867 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1869 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1871 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1873 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1875 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1877 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1879 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1881 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1883 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1885 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1887 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1889 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1891 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1893 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1895 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1897 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1899 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1901 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1903 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1905 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1907 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1909 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1911 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1913 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1915 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1917 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1919 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1921 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1923 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1925 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1927 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1929 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1931 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1933 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1935 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1937 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1939 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1941 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1943 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1945 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1947 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1949 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1951 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1953 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1955 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1957 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1959 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1961 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1963 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1965 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1967 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1969 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1971 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1973 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1975 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1977 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1979 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1981 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1983 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1985 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1987 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1989 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1991 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1993 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1995 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1997 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~1999 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2001 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2003 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2005 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2007 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2009 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2011 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2013 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2015 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2017 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2019 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2021 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2023 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2025 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2027 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2029 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2031 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2033 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2035 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2037 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2039 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2041 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2043 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2045 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2047 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2049 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2051 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2053 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2055 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2057 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2059 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2061 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2063 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2065 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2067 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2069 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2071 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2073 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2075 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2077 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2079 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2081 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2083 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2085 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2087 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2089 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2091 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2093 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2095 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2097 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2099 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2101 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2103 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2105 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2107 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2109 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2111 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2113 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2115 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2117 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2119 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2121 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2123 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2125 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2127 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2129 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2131 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2133 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2135 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2137 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2139 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2141 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2143 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2145 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2147 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2149 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2151 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2153 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2155 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2157 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2159 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2161 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2163 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2165 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2167 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2169 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2171 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2173 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2175 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2177 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2179 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2181 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2183 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2185 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2187 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2189 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2191 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2193 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2195 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2197 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2199 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2201 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2203 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2205 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2207 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2209 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2211 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2213 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2215 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2217 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2219 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2221 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2223 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2225 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2227 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2229 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2231 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2233 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2235 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2237 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2239 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2241 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2243 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2245 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2247 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2249 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2251 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2253 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2255 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2257 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2259 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2261 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2263 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2265 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2267 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2269 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2271 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2273 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2275 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2277 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2279 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2281 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2283 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2285 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2287 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2289 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2291 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2293 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2295 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2297 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2299 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2301 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2303 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2305 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2307 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2309 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2311 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2313 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2315 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2317 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2319 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2321 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2323 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2325 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2327 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2329 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2331 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2333 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2335 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2337 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2339 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2341 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2343 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2345 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2347 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2349 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2351 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2353 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2355 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2357 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2359 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2361 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2363 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2365 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2367 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2369 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2371 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2373 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2375 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2377 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2379 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2381 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2383 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2385 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2387 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2389 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2391 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2393 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2395 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2397 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2399 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2401 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2403 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2405 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2407 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2409 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2411 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2413 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2415 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2417 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2419 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2421 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2423 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2425 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2427 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2429 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2431 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2433 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2435 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2437 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2439 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2441 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2443 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2445 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2447 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2449 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2451 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2453 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2455 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2457 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2459 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2461 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2463 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2465 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2467 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2469 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2471 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2473 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2475 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2477 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2479 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2481 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2483 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2485 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2487 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2489 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2491 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2493 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2495 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2497 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2499 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2501 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2503 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2505 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2507 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2509 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2511 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2513 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2515 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2517 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2519 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2521 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2523 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2525 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2527 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2529 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2531 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2533 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2535 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2537 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2539 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2541 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2543 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2545 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2547 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2549 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2551 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2553 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2555 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2557 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2559 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2561 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2563 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2565 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2567 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2569 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2571 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2573 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2575 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2577 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2579 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2581 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2583 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2585 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2587 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2589 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2591 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2593 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2595 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2597 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2599 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2601 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2603 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2605 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2607 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2609 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2611 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2613 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2615 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2617 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2619 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2621 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2623 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2625 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2627 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2629 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2631 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2633 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2635 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2637 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2639 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2641 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2643 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2645 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2647 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2649 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2651 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2653 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2655 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2657 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2659 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2661 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2663 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2665 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2667 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2669 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2671 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2673 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2675 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2677 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2679 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2681 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2683 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2685 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2687 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2689 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2691 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2693 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2695 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2697 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2699 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2701 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2703 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2705 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2707 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2709 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2711 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2713 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2715 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2717 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2719 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2721 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2723 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2725 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2727 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2729 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2731 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2733 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2735 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2737 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2739 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2741 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2743 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2745 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2747 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2749 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2751 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2753 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2755 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2757 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2759 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2761 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2763 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2765 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2767 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2769 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2771 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2773 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2775 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2777 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2779 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2781 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2783 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2785 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2787 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2789 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2791 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2793 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2795 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2797 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2799 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2801 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2803 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2805 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2807 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2809 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2811 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2813 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2815 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2817 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2819 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2821 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2823 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2825 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2827 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2829 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2831 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2833 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2835 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2837 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2839 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2841 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2843 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2845 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2847 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2849 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2851 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2853 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2855 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2857 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2859 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2861 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2863 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2865 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2867 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2869 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2871 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2873 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2875 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2877 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2879 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2881 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2883 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2885 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2887 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2889 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2891 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2893 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2895 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2897 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2899 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2901 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2903 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2905 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2907 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2909 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2911 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2913 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2915 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2917 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2919 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2921 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2923 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2925 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2927 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2929 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2931 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2933 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2935 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2937 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2939 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2941 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2943 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2945 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2947 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2949 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2951 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2953 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2955 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2957 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2959 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2961 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2963 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2965 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2967 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2969 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2971 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2973 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2975 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2977 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2979 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2981 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2983 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2985 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2987 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2989 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2991 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2993 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2995 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2997 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~2999 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3001 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3003 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3005 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3007 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3009 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3011 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3013 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3015 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3017 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3019 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3021 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3023 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3025 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3027 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3029 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3031 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3033 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3035 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3037 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3039 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3041 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3043 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3045 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3047 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3049 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3051 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3053 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3055 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3057 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3059 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3061 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3063 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3065 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3067 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3069 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3071 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3073 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3075 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3077 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3079 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3081 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3083 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3085 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3087 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3089 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3091 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3093 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3095 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3097 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3099 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3101 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3103 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3105 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3107 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3109 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3111 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3113 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3115 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3117 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3119 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3121 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3123 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3125 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3127 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3129 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3131 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3133 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3135 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3137 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3139 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3141 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3143 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3145 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3147 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3149 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3151 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3153 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3155 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3157 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3159 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3161 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3163 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3165 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3167 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3169 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3171 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3173 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3175 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3177 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3179 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3181 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3183 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3185 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3187 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3189 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3191 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3193 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3195 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3197 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3199 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3201 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3203 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3205 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3207 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3209 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3211 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3213 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3215 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3217 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3219 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3221 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3223 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3225 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3227 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3229 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3231 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3233 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3235 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3237 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3239 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3241 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3243 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3245 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3247 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3249 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3251 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3253 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3255 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3257 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3259 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3261 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3263 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3265 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3267 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3269 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3271 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3273 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3275 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3277 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3279 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3281 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3283 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3285 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3287 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3289 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3291 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3293 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3295 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3297 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3299 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3301 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3303 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3305 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3307 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3309 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3311 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3313 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3315 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3317 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3319 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3321 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3323 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3325 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3327 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3329 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3331 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3333 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3335 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3337 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3339 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3341 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3343 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3345 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3347 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3349 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3351 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3353 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3355 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3357 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3359 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3361 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3363 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3365 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3367 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3369 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3371 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3373 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3375 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3377 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3379 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3381 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3383 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3385 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3387 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3389 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3391 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3393 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3395 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3397 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3399 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3401 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3403 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3405 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3407 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3409 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3411 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3413 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3415 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3417 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3419 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3421 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3423 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3425 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3427 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3429 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3431 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3433 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3435 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3437 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3439 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3441 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3443 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3445 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3447 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3449 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3451 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3453 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3455 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3457 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3459 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3461 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3463 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3465 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3467 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3469 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3471 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3473 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3475 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3477 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3479 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3481 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3483 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3485 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3487 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3489 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3491 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3493 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3495 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3497 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3499 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3501 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3503 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3505 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3507 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3509 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3511 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3513 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3515 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3517 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3519 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3521 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3523 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3525 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3527 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3529 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3531 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3533 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3535 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3537 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3539 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3541 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3543 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3545 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3547 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3549 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3551 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3553 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3555 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3557 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3559 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3561 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3563 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3565 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3567 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3569 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3571 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3573 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3575 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3577 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3579 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3581 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3583 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3585 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3587 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3589 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3591 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3593 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3595 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3597 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3599 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3601 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3603 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3605 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3607 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3609 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3611 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3613 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3615 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3617 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3619 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3621 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3623 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3625 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3627 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3629 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3631 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3633 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3635 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3637 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3639 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3641 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3643 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3645 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3647 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3649 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3651 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3653 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3655 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3657 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3659 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3661 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3663 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3665 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3667 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3669 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3671 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3673 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3675 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3677 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3679 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3681 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3683 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3685 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3687 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3689 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3691 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3693 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3695 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3697 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3699 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3701 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3703 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3705 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3707 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3709 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3711 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3713 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3715 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3717 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3719 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3721 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3723 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3725 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3727 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3729 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3731 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3733 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3735 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3737 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3739 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3741 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3743 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3745 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3747 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3749 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3751 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3753 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3755 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3757 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3759 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3761 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3763 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3765 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3767 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3769 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3771 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3773 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3775 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3777 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3779 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3781 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3783 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3785 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3787 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3789 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3791 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3793 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3795 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3797 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3799 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3801 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3803 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3805 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3807 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3809 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3811 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3813 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3815 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3817 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3819 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3821 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3823 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3825 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3827 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3829 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3831 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3833 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3835 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3837 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3839 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3841 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3843 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3845 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3847 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3849 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3851 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3853 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3855 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3857 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3859 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3861 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3863 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3865 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3867 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3869 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3871 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3873 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3875 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3877 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3879 ; Stuck at GND due to stuck port data_in ; +; ram:RAM|mem~3881 ; Stuck at GND due to stuck port data_in ; +; Total Number of Removed Registers = 5152 ; ; ++------------------------------------------+---------------------------------------------+ +* Table truncated at 5000 items. To change the number of removed registers reported, set the "Number of Removed Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++------------------------------+--------------------------------+-------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++------------------------------+--------------------------------+-------------------------------------------------------------------+ +; instruction_counter:PC|pc[0] ; Stuck at GND ; register_file:REGS|regs[0][3], register_file:REGS|regs[1][3], ; +; ; due to stuck port clock_enable ; register_file:REGS|regs[2][3], register_file:REGS|regs[3][3], ; +; ; ; register_file:REGS|regs[4][3], register_file:REGS|regs[5][3], ; +; ; ; register_file:REGS|regs[6][3], register_file:REGS|regs[7][3], ; +; ; ; register_file:REGS|regs[8][3], register_file:REGS|regs[9][3], ; +; ; ; register_file:REGS|regs[10][3], register_file:REGS|regs[11][3], ; +; ; ; register_file:REGS|regs[12][3], register_file:REGS|regs[13][3], ; +; ; ; register_file:REGS|regs[14][3], register_file:REGS|regs[15][3], ; +; ; ; register_file:REGS|regs[16][3], register_file:REGS|regs[17][3], ; +; ; ; register_file:REGS|regs[18][3], register_file:REGS|regs[19][3], ; +; ; ; register_file:REGS|regs[20][3], register_file:REGS|regs[21][3], ; +; ; ; register_file:REGS|regs[22][3], register_file:REGS|regs[23][3], ; +; ; ; register_file:REGS|regs[24][3], register_file:REGS|regs[25][3], ; +; ; ; register_file:REGS|regs[26][3], register_file:REGS|regs[27][3], ; +; ; ; register_file:REGS|regs[28][3], register_file:REGS|regs[29][3], ; +; ; ; register_file:REGS|regs[30][3], register_file:REGS|regs[31][3], ; +; ; ; register_file:REGS|regs[0][19], register_file:REGS|regs[1][19], ; +; ; ; register_file:REGS|regs[2][19], register_file:REGS|regs[3][19], ; +; ; ; register_file:REGS|regs[4][19], register_file:REGS|regs[5][19], ; +; ; ; register_file:REGS|regs[6][19], register_file:REGS|regs[7][19], ; +; ; ; register_file:REGS|regs[8][19], register_file:REGS|regs[9][19], ; +; ; ; register_file:REGS|regs[10][19], register_file:REGS|regs[11][19], ; +; ; ; register_file:REGS|regs[12][19], register_file:REGS|regs[13][19], ; +; ; ; register_file:REGS|regs[14][19], register_file:REGS|regs[15][19], ; +; ; ; register_file:REGS|regs[16][19], register_file:REGS|regs[17][19], ; +; ; ; register_file:REGS|regs[18][19], register_file:REGS|regs[19][19], ; +; ; ; register_file:REGS|regs[20][19], register_file:REGS|regs[21][19], ; +; ; ; register_file:REGS|regs[22][19], register_file:REGS|regs[23][19], ; +; ; ; register_file:REGS|regs[24][19], register_file:REGS|regs[25][19], ; +; ; ; register_file:REGS|regs[26][19], register_file:REGS|regs[27][19], ; +; ; ; register_file:REGS|regs[28][19], register_file:REGS|regs[29][19], ; +; ; ; register_file:REGS|regs[30][19], register_file:REGS|regs[31][19], ; +; ; ; register_file:REGS|regs[0][2], register_file:REGS|regs[1][2], ; +; ; ; register_file:REGS|regs[2][2], register_file:REGS|regs[3][2], ; +; ; ; register_file:REGS|regs[4][2], register_file:REGS|regs[5][2], ; +; ; ; register_file:REGS|regs[6][2], register_file:REGS|regs[7][2], ; +; ; ; register_file:REGS|regs[8][2], register_file:REGS|regs[9][2], ; +; ; ; register_file:REGS|regs[10][2], register_file:REGS|regs[11][2], ; +; ; ; register_file:REGS|regs[12][2], register_file:REGS|regs[13][2], ; +; ; ; register_file:REGS|regs[14][2], register_file:REGS|regs[15][2], ; +; ; ; register_file:REGS|regs[16][2], register_file:REGS|regs[17][2], ; +; ; ; register_file:REGS|regs[18][2], register_file:REGS|regs[19][2], ; +; ; ; register_file:REGS|regs[20][2], register_file:REGS|regs[21][2], ; +; ; ; register_file:REGS|regs[22][2], register_file:REGS|regs[23][2], ; +; ; ; register_file:REGS|regs[24][2], register_file:REGS|regs[25][2], ; +; ; ; register_file:REGS|regs[26][2], register_file:REGS|regs[27][2], ; +; ; ; register_file:REGS|regs[28][2], register_file:REGS|regs[29][2], ; +; ; ; register_file:REGS|regs[30][2], register_file:REGS|regs[31][2], ; +; ; ; register_file:REGS|regs[0][18], register_file:REGS|regs[1][18], ; +; ; ; register_file:REGS|regs[2][18], register_file:REGS|regs[3][18], ; +; ; ; register_file:REGS|regs[4][18], register_file:REGS|regs[5][18], ; +; ; ; register_file:REGS|regs[6][18], register_file:REGS|regs[7][18], ; +; ; ; register_file:REGS|regs[8][18], register_file:REGS|regs[9][18], ; +; ; ; register_file:REGS|regs[10][18], register_file:REGS|regs[11][18], ; +; ; ; register_file:REGS|regs[12][18], register_file:REGS|regs[13][18], ; +; ; ; register_file:REGS|regs[14][18], register_file:REGS|regs[15][18], ; +; ; ; register_file:REGS|regs[16][18], register_file:REGS|regs[17][18], ; +; ; ; register_file:REGS|regs[18][18], register_file:REGS|regs[19][18], ; +; ; ; register_file:REGS|regs[20][18], register_file:REGS|regs[21][18], ; +; ; ; register_file:REGS|regs[22][18], register_file:REGS|regs[23][18], ; +; ; ; register_file:REGS|regs[24][18], register_file:REGS|regs[25][18], ; +; ; ; register_file:REGS|regs[26][18], register_file:REGS|regs[27][18], ; +; ; ; register_file:REGS|regs[28][18], register_file:REGS|regs[29][18], ; +; ; ; register_file:REGS|regs[30][18], register_file:REGS|regs[31][18], ; +; ; ; register_file:REGS|regs[0][17], register_file:REGS|regs[1][17], ; +; ; ; register_file:REGS|regs[2][17], register_file:REGS|regs[3][17], ; +; ; ; register_file:REGS|regs[4][17], register_file:REGS|regs[5][17], ; +; ; ; register_file:REGS|regs[6][17], register_file:REGS|regs[7][17], ; +; ; ; register_file:REGS|regs[8][17], register_file:REGS|regs[9][17], ; +; ; ; register_file:REGS|regs[10][17], register_file:REGS|regs[11][17], ; +; ; ; register_file:REGS|regs[12][17], register_file:REGS|regs[13][17], ; +; ; ; register_file:REGS|regs[14][17], register_file:REGS|regs[15][17], ; +; ; ; register_file:REGS|regs[16][17], register_file:REGS|regs[17][17], ; +; ; ; register_file:REGS|regs[18][17], register_file:REGS|regs[19][17], ; +; ; ; register_file:REGS|regs[20][17], register_file:REGS|regs[21][17], ; +; ; ; register_file:REGS|regs[22][17], register_file:REGS|regs[23][17], ; +; ; ; register_file:REGS|regs[24][17], register_file:REGS|regs[25][17], ; +; ; ; register_file:REGS|regs[26][17], register_file:REGS|regs[27][17], ; +; ; ; register_file:REGS|regs[28][17], register_file:REGS|regs[29][17], ; +; ; ; register_file:REGS|regs[30][17], register_file:REGS|regs[31][17], ; +; ; ; register_file:REGS|regs[0][16], register_file:REGS|regs[1][16], ; +; ; ; register_file:REGS|regs[2][16], register_file:REGS|regs[3][16], ; +; ; ; register_file:REGS|regs[4][16], register_file:REGS|regs[5][16], ; +; ; ; register_file:REGS|regs[6][16], register_file:REGS|regs[7][16], ; +; ; ; register_file:REGS|regs[8][16], register_file:REGS|regs[9][16], ; +; ; ; register_file:REGS|regs[10][16], register_file:REGS|regs[11][16], ; +; ; ; register_file:REGS|regs[12][16], register_file:REGS|regs[13][16], ; +; ; ; register_file:REGS|regs[14][16], register_file:REGS|regs[15][16], ; +; ; ; register_file:REGS|regs[16][16], register_file:REGS|regs[17][16], ; +; ; ; register_file:REGS|regs[18][16], register_file:REGS|regs[19][16], ; +; ; ; register_file:REGS|regs[20][16], register_file:REGS|regs[21][16], ; +; ; ; register_file:REGS|regs[22][16], register_file:REGS|regs[23][16], ; +; ; ; register_file:REGS|regs[24][16], register_file:REGS|regs[25][16], ; +; ; ; register_file:REGS|regs[26][16], register_file:REGS|regs[27][16], ; +; ; ; register_file:REGS|regs[28][16], register_file:REGS|regs[29][16], ; +; ; ; register_file:REGS|regs[30][16], register_file:REGS|regs[31][16], ; +; ; ; register_file:REGS|regs[0][7], register_file:REGS|regs[1][7], ; +; ; ; register_file:REGS|regs[2][7], register_file:REGS|regs[3][7], ; +; ; ; register_file:REGS|regs[4][7], register_file:REGS|regs[5][7], ; +; ; ; register_file:REGS|regs[6][7], register_file:REGS|regs[7][7], ; +; ; ; register_file:REGS|regs[8][7], register_file:REGS|regs[9][7], ; +; ; ; register_file:REGS|regs[10][7], register_file:REGS|regs[11][7], ; +; ; ; register_file:REGS|regs[12][7], register_file:REGS|regs[13][7], ; +; ; ; register_file:REGS|regs[14][7], register_file:REGS|regs[15][7], ; +; ; ; register_file:REGS|regs[16][7], register_file:REGS|regs[17][7], ; +; ; ; register_file:REGS|regs[18][7], register_file:REGS|regs[19][7], ; +; ; ; register_file:REGS|regs[20][7], register_file:REGS|regs[21][7], ; +; ; ; register_file:REGS|regs[22][7], register_file:REGS|regs[23][7], ; +; ; ; register_file:REGS|regs[24][7], register_file:REGS|regs[25][7], ; +; ; ; register_file:REGS|regs[26][7], register_file:REGS|regs[27][7], ; +; ; ; register_file:REGS|regs[28][7], register_file:REGS|regs[29][7], ; +; ; ; register_file:REGS|regs[30][7], register_file:REGS|regs[31][7], ; +; ; ; register_file:REGS|regs[0][23], register_file:REGS|regs[1][23], ; +; ; ; register_file:REGS|regs[2][23], register_file:REGS|regs[3][23], ; +; ; ; register_file:REGS|regs[4][23], register_file:REGS|regs[5][23], ; +; ; ; register_file:REGS|regs[6][23], register_file:REGS|regs[7][23], ; +; ; ; register_file:REGS|regs[8][23], register_file:REGS|regs[9][23], ; +; ; ; register_file:REGS|regs[10][23], register_file:REGS|regs[11][23], ; +; ; ; register_file:REGS|regs[12][23], register_file:REGS|regs[13][23], ; +; ; ; register_file:REGS|regs[14][23], register_file:REGS|regs[15][23], ; +; ; ; register_file:REGS|regs[16][23], register_file:REGS|regs[17][23], ; +; ; ; register_file:REGS|regs[18][23], register_file:REGS|regs[19][23], ; +; ; ; register_file:REGS|regs[20][23], register_file:REGS|regs[21][23], ; +; ; ; register_file:REGS|regs[22][23], register_file:REGS|regs[23][23], ; +; ; ; register_file:REGS|regs[24][23], register_file:REGS|regs[25][23], ; +; ; ; register_file:REGS|regs[26][23], register_file:REGS|regs[27][23], ; +; ; ; register_file:REGS|regs[28][23], register_file:REGS|regs[29][23], ; +; ; ; register_file:REGS|regs[30][23], register_file:REGS|regs[31][23], ; +; ; ; register_file:REGS|regs[0][6], register_file:REGS|regs[1][6], ; +; ; ; register_file:REGS|regs[2][6], register_file:REGS|regs[3][6], ; +; ; ; register_file:REGS|regs[4][6], register_file:REGS|regs[5][6], ; +; ; ; register_file:REGS|regs[6][6], register_file:REGS|regs[7][6], ; +; ; ; register_file:REGS|regs[8][6], register_file:REGS|regs[9][6], ; +; ; ; register_file:REGS|regs[10][6], register_file:REGS|regs[11][6], ; +; ; ; register_file:REGS|regs[12][6], register_file:REGS|regs[13][6], ; +; ; ; register_file:REGS|regs[14][6], register_file:REGS|regs[15][6], ; +; ; ; register_file:REGS|regs[16][6], register_file:REGS|regs[17][6], ; +; ; ; register_file:REGS|regs[18][6], register_file:REGS|regs[19][6], ; +; ; ; register_file:REGS|regs[20][6], register_file:REGS|regs[21][6], ; +; ; ; register_file:REGS|regs[22][6], register_file:REGS|regs[23][6], ; +; ; ; register_file:REGS|regs[24][6], register_file:REGS|regs[25][6], ; +; ; ; register_file:REGS|regs[26][6], register_file:REGS|regs[27][6], ; +; ; ; register_file:REGS|regs[28][6], register_file:REGS|regs[29][6], ; +; ; ; register_file:REGS|regs[30][6], register_file:REGS|regs[31][6], ; +; ; ; register_file:REGS|regs[0][22], register_file:REGS|regs[1][22], ; +; ; ; register_file:REGS|regs[2][22], register_file:REGS|regs[3][22], ; +; ; ; register_file:REGS|regs[4][22], register_file:REGS|regs[5][22], ; +; ; ; register_file:REGS|regs[6][22], register_file:REGS|regs[7][22], ; +; ; ; register_file:REGS|regs[8][22], register_file:REGS|regs[9][22], ; +; ; ; register_file:REGS|regs[10][22], register_file:REGS|regs[11][22], ; +; ; ; register_file:REGS|regs[12][22], register_file:REGS|regs[13][22], ; +; ; ; register_file:REGS|regs[14][22], register_file:REGS|regs[15][22], ; +; ; ; register_file:REGS|regs[16][22], register_file:REGS|regs[17][22], ; +; ; ; register_file:REGS|regs[18][22], register_file:REGS|regs[19][22], ; +; ; ; register_file:REGS|regs[20][22], register_file:REGS|regs[21][22], ; +; ; ; register_file:REGS|regs[22][22], register_file:REGS|regs[23][22], ; +; ; ; register_file:REGS|regs[24][22], register_file:REGS|regs[25][22], ; +; ; ; register_file:REGS|regs[26][22], register_file:REGS|regs[27][22], ; +; ; ; register_file:REGS|regs[28][22], register_file:REGS|regs[29][22], ; +; ; ; register_file:REGS|regs[30][22], register_file:REGS|regs[31][22], ; +; ; ; register_file:REGS|regs[0][5], register_file:REGS|regs[1][5], ; +; ; ; register_file:REGS|regs[2][5], register_file:REGS|regs[3][5], ; +; ; ; register_file:REGS|regs[4][5], register_file:REGS|regs[5][5], ; +; ; ; register_file:REGS|regs[6][5], register_file:REGS|regs[7][5], ; +; ; ; register_file:REGS|regs[8][5], register_file:REGS|regs[9][5], ; +; ; ; register_file:REGS|regs[10][5], register_file:REGS|regs[11][5], ; +; ; ; register_file:REGS|regs[12][5], register_file:REGS|regs[13][5], ; +; ; ; register_file:REGS|regs[14][5], register_file:REGS|regs[15][5], ; +; ; ; register_file:REGS|regs[16][5], register_file:REGS|regs[17][5], ; +; ; ; register_file:REGS|regs[18][5], register_file:REGS|regs[19][5], ; +; ; ; register_file:REGS|regs[20][5], register_file:REGS|regs[21][5], ; +; ; ; register_file:REGS|regs[22][5], register_file:REGS|regs[23][5], ; +; ; ; register_file:REGS|regs[24][5], register_file:REGS|regs[25][5], ; +; ; ; register_file:REGS|regs[26][5], register_file:REGS|regs[27][5], ; +; ; ; register_file:REGS|regs[28][5], register_file:REGS|regs[29][5], ; +; ; ; register_file:REGS|regs[30][5], register_file:REGS|regs[31][5], ; +; ; ; register_file:REGS|regs[0][21], register_file:REGS|regs[1][21], ; +; ; ; register_file:REGS|regs[2][21], register_file:REGS|regs[3][21], ; +; ; ; register_file:REGS|regs[4][21], register_file:REGS|regs[5][21], ; +; ; ; register_file:REGS|regs[6][21], register_file:REGS|regs[7][21], ; +; ; ; register_file:REGS|regs[8][21], register_file:REGS|regs[9][21], ; +; ; ; register_file:REGS|regs[10][21], register_file:REGS|regs[11][21], ; +; ; ; register_file:REGS|regs[12][21], register_file:REGS|regs[13][21], ; +; ; ; register_file:REGS|regs[14][21], register_file:REGS|regs[15][21], ; +; ; ; register_file:REGS|regs[16][21], register_file:REGS|regs[17][21], ; +; ; ; register_file:REGS|regs[18][21], register_file:REGS|regs[19][21], ; +; ; ; register_file:REGS|regs[20][21], register_file:REGS|regs[21][21], ; +; ; ; register_file:REGS|regs[22][21], register_file:REGS|regs[23][21], ; +; ; ; register_file:REGS|regs[24][21], register_file:REGS|regs[25][21], ; +; ; ; register_file:REGS|regs[26][21], register_file:REGS|regs[27][21], ; +; ; ; register_file:REGS|regs[28][21], register_file:REGS|regs[29][21], ; +; ; ; register_file:REGS|regs[30][21], register_file:REGS|regs[31][21], ; +; ; ; register_file:REGS|regs[0][4], register_file:REGS|regs[1][4], ; +; ; ; register_file:REGS|regs[2][4], register_file:REGS|regs[3][4], ; +; ; ; register_file:REGS|regs[4][4], register_file:REGS|regs[5][4], ; +; ; ; register_file:REGS|regs[6][4], register_file:REGS|regs[7][4], ; +; ; ; register_file:REGS|regs[8][4], register_file:REGS|regs[9][4], ; +; ; ; register_file:REGS|regs[10][4], register_file:REGS|regs[11][4], ; +; ; ; register_file:REGS|regs[12][4], register_file:REGS|regs[13][4], ; +; ; ; register_file:REGS|regs[14][4], register_file:REGS|regs[15][4], ; +; ; ; register_file:REGS|regs[16][4], register_file:REGS|regs[17][4], ; +; ; ; register_file:REGS|regs[18][4], register_file:REGS|regs[19][4], ; +; ; ; register_file:REGS|regs[20][4], register_file:REGS|regs[21][4], ; +; ; ; register_file:REGS|regs[22][4], register_file:REGS|regs[23][4], ; +; ; ; register_file:REGS|regs[24][4], register_file:REGS|regs[25][4], ; +; ; ; register_file:REGS|regs[26][4], register_file:REGS|regs[27][4], ; +; ; ; register_file:REGS|regs[28][4], register_file:REGS|regs[29][4], ; +; ; ; register_file:REGS|regs[30][4], register_file:REGS|regs[31][4], ; +; ; ; register_file:REGS|regs[0][20], register_file:REGS|regs[1][20], ; +; ; ; register_file:REGS|regs[2][20], register_file:REGS|regs[3][20], ; +; ; ; register_file:REGS|regs[4][20], register_file:REGS|regs[5][20], ; +; ; ; register_file:REGS|regs[6][20], register_file:REGS|regs[7][20], ; +; ; ; register_file:REGS|regs[8][20], register_file:REGS|regs[9][20], ; +; ; ; register_file:REGS|regs[10][20], register_file:REGS|regs[11][20], ; +; ; ; register_file:REGS|regs[12][20], register_file:REGS|regs[13][20], ; +; ; ; register_file:REGS|regs[14][20], register_file:REGS|regs[15][20], ; +; ; ; register_file:REGS|regs[16][20], register_file:REGS|regs[17][20], ; +; ; ; register_file:REGS|regs[18][20], register_file:REGS|regs[19][20], ; +; ; ; register_file:REGS|regs[20][20], register_file:REGS|regs[21][20], ; +; ; ; register_file:REGS|regs[22][20], register_file:REGS|regs[23][20], ; +; ; ; register_file:REGS|regs[24][20], register_file:REGS|regs[25][20], ; +; ; ; register_file:REGS|regs[26][20], register_file:REGS|regs[27][20], ; +; ; ; register_file:REGS|regs[28][20], register_file:REGS|regs[29][20], ; +; ; ; register_file:REGS|regs[30][20], register_file:REGS|regs[31][20], ; +; ; ; register_file:REGS|regs[0][11], register_file:REGS|regs[1][11], ; +; ; ; register_file:REGS|regs[2][11], register_file:REGS|regs[3][11], ; +; ; ; register_file:REGS|regs[4][11], register_file:REGS|regs[5][11], ; +; ; ; register_file:REGS|regs[6][11], register_file:REGS|regs[7][11], ; +; ; ; register_file:REGS|regs[8][11], register_file:REGS|regs[9][11], ; +; ; ; register_file:REGS|regs[10][11], register_file:REGS|regs[11][11], ; +; ; ; register_file:REGS|regs[12][11], register_file:REGS|regs[13][11], ; +; ; ; register_file:REGS|regs[14][11], register_file:REGS|regs[15][11], ; +; ; ; register_file:REGS|regs[16][11], register_file:REGS|regs[17][11], ; +; ; ; register_file:REGS|regs[18][11], register_file:REGS|regs[19][11], ; +; ; ; register_file:REGS|regs[20][11], register_file:REGS|regs[21][11], ; +; ; ; register_file:REGS|regs[22][11], register_file:REGS|regs[23][11], ; +; ; ; register_file:REGS|regs[24][11], register_file:REGS|regs[25][11], ; +; ; ; register_file:REGS|regs[26][11], register_file:REGS|regs[27][11], ; +; ; ; register_file:REGS|regs[28][11], register_file:REGS|regs[29][11], ; +; ; ; register_file:REGS|regs[30][11], register_file:REGS|regs[31][11], ; +; ; ; register_file:REGS|regs[0][27], register_file:REGS|regs[1][27], ; +; ; ; register_file:REGS|regs[2][27], register_file:REGS|regs[3][27], ; +; ; ; register_file:REGS|regs[4][27], register_file:REGS|regs[5][27], ; +; ; ; register_file:REGS|regs[6][27], register_file:REGS|regs[7][27], ; +; ; ; register_file:REGS|regs[8][27], register_file:REGS|regs[9][27], ; +; ; ; register_file:REGS|regs[10][27], register_file:REGS|regs[11][27], ; +; ; ; register_file:REGS|regs[12][27], register_file:REGS|regs[13][27], ; +; ; ; register_file:REGS|regs[14][27], register_file:REGS|regs[15][27], ; +; ; ; register_file:REGS|regs[16][27], register_file:REGS|regs[17][27], ; +; ; ; register_file:REGS|regs[18][27], register_file:REGS|regs[19][27], ; +; ; ; register_file:REGS|regs[20][27], register_file:REGS|regs[21][27], ; +; ; ; register_file:REGS|regs[22][27], register_file:REGS|regs[23][27], ; +; ; ; register_file:REGS|regs[24][27], register_file:REGS|regs[25][27], ; +; ; ; register_file:REGS|regs[26][27], register_file:REGS|regs[27][27], ; +; ; ; register_file:REGS|regs[28][27], register_file:REGS|regs[29][27], ; +; ; ; register_file:REGS|regs[30][27], register_file:REGS|regs[31][27], ; +; ; ; register_file:REGS|regs[0][10], register_file:REGS|regs[1][10], ; +; ; ; register_file:REGS|regs[2][10], register_file:REGS|regs[3][10], ; +; ; ; register_file:REGS|regs[4][10], register_file:REGS|regs[5][10], ; +; ; ; register_file:REGS|regs[6][10], register_file:REGS|regs[7][10], ; +; ; ; register_file:REGS|regs[8][10], register_file:REGS|regs[9][10], ; +; ; ; register_file:REGS|regs[10][10], register_file:REGS|regs[11][10], ; +; ; ; register_file:REGS|regs[12][10], register_file:REGS|regs[13][10], ; +; ; ; register_file:REGS|regs[14][10], register_file:REGS|regs[15][10], ; +; ; ; register_file:REGS|regs[16][10], register_file:REGS|regs[17][10], ; +; ; ; register_file:REGS|regs[18][10], register_file:REGS|regs[19][10], ; +; ; ; register_file:REGS|regs[20][10], register_file:REGS|regs[21][10], ; +; ; ; register_file:REGS|regs[22][10], register_file:REGS|regs[23][10], ; +; ; ; register_file:REGS|regs[24][10], register_file:REGS|regs[25][10], ; +; ; ; register_file:REGS|regs[26][10], register_file:REGS|regs[27][10], ; +; ; ; register_file:REGS|regs[28][10], register_file:REGS|regs[29][10], ; +; ; ; register_file:REGS|regs[30][10], register_file:REGS|regs[31][10], ; +; ; ; register_file:REGS|regs[0][26], register_file:REGS|regs[1][26], ; +; ; ; register_file:REGS|regs[2][26], register_file:REGS|regs[3][26], ; +; ; ; register_file:REGS|regs[4][26], register_file:REGS|regs[5][26], ; +; ; ; register_file:REGS|regs[6][26], register_file:REGS|regs[7][26], ; +; ; ; register_file:REGS|regs[8][26], register_file:REGS|regs[9][26], ; +; ; ; register_file:REGS|regs[10][26], register_file:REGS|regs[11][26], ; +; ; ; register_file:REGS|regs[12][26], register_file:REGS|regs[13][26], ; +; ; ; register_file:REGS|regs[14][26], register_file:REGS|regs[15][26], ; +; ; ; register_file:REGS|regs[16][26], register_file:REGS|regs[17][26], ; +; ; ; register_file:REGS|regs[18][26], register_file:REGS|regs[19][26], ; +; ; ; register_file:REGS|regs[20][26], register_file:REGS|regs[21][26], ; +; ; ; register_file:REGS|regs[22][26], register_file:REGS|regs[23][26], ; +; ; ; register_file:REGS|regs[24][26], register_file:REGS|regs[25][26], ; +; ; ; register_file:REGS|regs[26][26], register_file:REGS|regs[27][26], ; +; ; ; register_file:REGS|regs[28][26], register_file:REGS|regs[29][26], ; +; ; ; register_file:REGS|regs[30][26], register_file:REGS|regs[31][26], ; +; ; ; register_file:REGS|regs[0][9], register_file:REGS|regs[1][9], ; +; ; ; register_file:REGS|regs[2][9], register_file:REGS|regs[3][9], ; +; ; ; register_file:REGS|regs[4][9], register_file:REGS|regs[5][9], ; +; ; ; register_file:REGS|regs[6][9], register_file:REGS|regs[7][9], ; +; ; ; register_file:REGS|regs[8][9], register_file:REGS|regs[9][9], ; +; ; ; register_file:REGS|regs[10][9], register_file:REGS|regs[11][9], ; +; ; ; register_file:REGS|regs[12][9], register_file:REGS|regs[13][9], ; +; ; ; register_file:REGS|regs[14][9], register_file:REGS|regs[15][9], ; +; ; ; register_file:REGS|regs[16][9], register_file:REGS|regs[17][9], ; +; ; ; register_file:REGS|regs[18][9], register_file:REGS|regs[19][9], ; +; ; ; register_file:REGS|regs[20][9], register_file:REGS|regs[21][9], ; +; ; ; register_file:REGS|regs[22][9], register_file:REGS|regs[23][9], ; +; ; ; register_file:REGS|regs[24][9], register_file:REGS|regs[25][9], ; +; ; ; register_file:REGS|regs[26][9], register_file:REGS|regs[27][9], ; +; ; ; register_file:REGS|regs[28][9], register_file:REGS|regs[29][9], ; +; ; ; register_file:REGS|regs[30][9], register_file:REGS|regs[31][9], ; +; ; ; register_file:REGS|regs[0][25], register_file:REGS|regs[1][25], ; +; ; ; register_file:REGS|regs[2][25], register_file:REGS|regs[3][25], ; +; ; ; register_file:REGS|regs[4][25], register_file:REGS|regs[5][25], ; +; ; ; register_file:REGS|regs[6][25], register_file:REGS|regs[7][25], ; +; ; ; register_file:REGS|regs[8][25], register_file:REGS|regs[9][25], ; +; ; ; register_file:REGS|regs[10][25], register_file:REGS|regs[11][25], ; +; ; ; register_file:REGS|regs[12][25], register_file:REGS|regs[13][25], ; +; ; ; register_file:REGS|regs[14][25], register_file:REGS|regs[15][25], ; +; ; ; register_file:REGS|regs[16][25], register_file:REGS|regs[17][25], ; +; ; ; register_file:REGS|regs[18][25], register_file:REGS|regs[19][25], ; +; ; ; register_file:REGS|regs[20][25], register_file:REGS|regs[21][25], ; +; ; ; register_file:REGS|regs[22][25], register_file:REGS|regs[23][25], ; +; ; ; register_file:REGS|regs[24][25], register_file:REGS|regs[25][25], ; +; ; ; register_file:REGS|regs[26][25], register_file:REGS|regs[27][25], ; +; ; ; register_file:REGS|regs[28][25], register_file:REGS|regs[29][25], ; +; ; ; register_file:REGS|regs[30][25], register_file:REGS|regs[31][25], ; +; ; ; register_file:REGS|regs[0][8], register_file:REGS|regs[1][8], ; +; ; ; register_file:REGS|regs[2][8], register_file:REGS|regs[3][8], ; +; ; ; register_file:REGS|regs[4][8], register_file:REGS|regs[5][8], ; +; ; ; register_file:REGS|regs[6][8], register_file:REGS|regs[7][8], ; +; ; ; register_file:REGS|regs[8][8], register_file:REGS|regs[9][8], ; +; ; ; register_file:REGS|regs[10][8], register_file:REGS|regs[11][8], ; +; ; ; register_file:REGS|regs[12][8], register_file:REGS|regs[13][8], ; +; ; ; register_file:REGS|regs[14][8], register_file:REGS|regs[15][8], ; +; ; ; register_file:REGS|regs[16][8], register_file:REGS|regs[17][8], ; +; ; ; register_file:REGS|regs[18][8], register_file:REGS|regs[19][8], ; +; ; ; register_file:REGS|regs[20][8], register_file:REGS|regs[21][8], ; +; ; ; register_file:REGS|regs[22][8], register_file:REGS|regs[23][8], ; +; ; ; register_file:REGS|regs[24][8], register_file:REGS|regs[25][8], ; +; ; ; register_file:REGS|regs[26][8], register_file:REGS|regs[27][8], ; +; ; ; register_file:REGS|regs[28][8], register_file:REGS|regs[29][8], ; +; ; ; register_file:REGS|regs[30][8], register_file:REGS|regs[31][8], ; +; ; ; register_file:REGS|regs[0][24], register_file:REGS|regs[1][24], ; +; ; ; register_file:REGS|regs[2][24], register_file:REGS|regs[3][24], ; +; ; ; register_file:REGS|regs[4][24], register_file:REGS|regs[5][24], ; +; ; ; register_file:REGS|regs[6][24], register_file:REGS|regs[7][24], ; +; ; ; register_file:REGS|regs[8][24], register_file:REGS|regs[9][24], ; +; ; ; register_file:REGS|regs[10][24], register_file:REGS|regs[11][24], ; +; ; ; register_file:REGS|regs[12][24], register_file:REGS|regs[13][24], ; +; ; ; register_file:REGS|regs[14][24], register_file:REGS|regs[15][24], ; +; ; ; register_file:REGS|regs[16][24], register_file:REGS|regs[17][24], ; +; ; ; register_file:REGS|regs[18][24], register_file:REGS|regs[19][24], ; +; ; ; register_file:REGS|regs[20][24], register_file:REGS|regs[21][24], ; +; ; ; register_file:REGS|regs[22][24], register_file:REGS|regs[23][24], ; +; ; ; register_file:REGS|regs[24][24], register_file:REGS|regs[25][24], ; +; ; ; register_file:REGS|regs[26][24], register_file:REGS|regs[27][24], ; +; ; ; register_file:REGS|regs[28][24], register_file:REGS|regs[29][24], ; +; ; ; register_file:REGS|regs[30][24], register_file:REGS|regs[31][24], ; +; ; ; register_file:REGS|regs[0][15], register_file:REGS|regs[1][15], ; +; ; ; register_file:REGS|regs[2][15], register_file:REGS|regs[3][15], ; +; ; ; register_file:REGS|regs[4][15], register_file:REGS|regs[5][15], ; +; ; ; register_file:REGS|regs[6][15], register_file:REGS|regs[7][15], ; +; ; ; register_file:REGS|regs[8][15], register_file:REGS|regs[9][15], ; +; ; ; register_file:REGS|regs[10][15], register_file:REGS|regs[11][15], ; +; ; ; register_file:REGS|regs[12][15], register_file:REGS|regs[13][15], ; +; ; ; register_file:REGS|regs[14][15], register_file:REGS|regs[15][15], ; +; ; ; register_file:REGS|regs[16][15], register_file:REGS|regs[17][15], ; +; ; ; register_file:REGS|regs[18][15], register_file:REGS|regs[19][15], ; +; ; ; register_file:REGS|regs[20][15], register_file:REGS|regs[21][15], ; +; ; ; register_file:REGS|regs[22][15], register_file:REGS|regs[23][15], ; +; ; ; register_file:REGS|regs[24][15], register_file:REGS|regs[25][15], ; +; ; ; register_file:REGS|regs[26][15], register_file:REGS|regs[27][15], ; +; ; ; register_file:REGS|regs[28][15], register_file:REGS|regs[29][15], ; +; ; ; register_file:REGS|regs[30][15], register_file:REGS|regs[31][15], ; +; ; ; register_file:REGS|regs[0][31], register_file:REGS|regs[1][31], ; +; ; ; register_file:REGS|regs[2][31], register_file:REGS|regs[3][31], ; +; ; ; register_file:REGS|regs[4][31], register_file:REGS|regs[5][31], ; +; ; ; register_file:REGS|regs[6][31], register_file:REGS|regs[7][31], ; +; ; ; register_file:REGS|regs[8][31], register_file:REGS|regs[9][31], ; +; ; ; register_file:REGS|regs[10][31], register_file:REGS|regs[11][31], ; +; ; ; register_file:REGS|regs[12][31], register_file:REGS|regs[13][31], ; +; ; ; register_file:REGS|regs[14][31], register_file:REGS|regs[15][31], ; +; ; ; register_file:REGS|regs[16][31], register_file:REGS|regs[17][31], ; +; ; ; register_file:REGS|regs[18][31], register_file:REGS|regs[19][31], ; +; ; ; register_file:REGS|regs[20][31], register_file:REGS|regs[21][31], ; +; ; ; register_file:REGS|regs[22][31], register_file:REGS|regs[23][31], ; +; ; ; register_file:REGS|regs[24][31], register_file:REGS|regs[25][31], ; +; ; ; register_file:REGS|regs[26][31], register_file:REGS|regs[27][31], ; +; ; ; register_file:REGS|regs[28][31], register_file:REGS|regs[29][31], ; +; ; ; register_file:REGS|regs[30][31], register_file:REGS|regs[31][31], ; +; ; ; register_file:REGS|regs[0][14], register_file:REGS|regs[1][14], ; +; ; ; register_file:REGS|regs[2][14], register_file:REGS|regs[3][14], ; +; ; ; register_file:REGS|regs[4][14], register_file:REGS|regs[5][14], ; +; ; ; register_file:REGS|regs[6][14], register_file:REGS|regs[7][14], ; +; ; ; register_file:REGS|regs[8][14], register_file:REGS|regs[9][14], ; +; ; ; register_file:REGS|regs[10][14], register_file:REGS|regs[11][14], ; +; ; ; register_file:REGS|regs[12][14], register_file:REGS|regs[13][14], ; +; ; ; register_file:REGS|regs[14][14], register_file:REGS|regs[15][14], ; +; ; ; register_file:REGS|regs[16][14], register_file:REGS|regs[17][14], ; +; ; ; register_file:REGS|regs[18][14], register_file:REGS|regs[19][14], ; +; ; ; register_file:REGS|regs[20][14], register_file:REGS|regs[21][14], ; +; ; ; register_file:REGS|regs[22][14], register_file:REGS|regs[23][14], ; +; ; ; register_file:REGS|regs[24][14], register_file:REGS|regs[25][14], ; +; ; ; register_file:REGS|regs[26][14], register_file:REGS|regs[27][14], ; +; ; ; register_file:REGS|regs[28][14], register_file:REGS|regs[29][14], ; +; ; ; register_file:REGS|regs[30][14], register_file:REGS|regs[31][14], ; +; ; ; register_file:REGS|regs[0][30], register_file:REGS|regs[1][30], ; +; ; ; register_file:REGS|regs[2][30], register_file:REGS|regs[3][30], ; +; ; ; register_file:REGS|regs[4][30], register_file:REGS|regs[5][30], ; +; ; ; register_file:REGS|regs[6][30], register_file:REGS|regs[7][30], ; +; ; ; register_file:REGS|regs[8][30], register_file:REGS|regs[9][30], ; +; ; ; register_file:REGS|regs[10][30], register_file:REGS|regs[11][30], ; +; ; ; register_file:REGS|regs[12][30], register_file:REGS|regs[13][30], ; +; ; ; register_file:REGS|regs[14][30], register_file:REGS|regs[15][30], ; +; ; ; register_file:REGS|regs[16][30], register_file:REGS|regs[17][30], ; +; ; ; register_file:REGS|regs[18][30], register_file:REGS|regs[19][30], ; +; ; ; register_file:REGS|regs[20][30], register_file:REGS|regs[21][30], ; +; ; ; register_file:REGS|regs[22][30], register_file:REGS|regs[23][30], ; +; ; ; register_file:REGS|regs[24][30], register_file:REGS|regs[25][30], ; +; ; ; register_file:REGS|regs[26][30], register_file:REGS|regs[27][30], ; +; ; ; register_file:REGS|regs[28][30], register_file:REGS|regs[29][30], ; +; ; ; register_file:REGS|regs[30][30], register_file:REGS|regs[31][30], ; +; ; ; register_file:REGS|regs[0][13], register_file:REGS|regs[1][13], ; +; ; ; register_file:REGS|regs[2][13], register_file:REGS|regs[3][13], ; +; ; ; register_file:REGS|regs[4][13], register_file:REGS|regs[5][13], ; +; ; ; register_file:REGS|regs[6][13], register_file:REGS|regs[7][13], ; +; ; ; register_file:REGS|regs[8][13], register_file:REGS|regs[9][13], ; +; ; ; register_file:REGS|regs[10][13], register_file:REGS|regs[11][13], ; +; ; ; register_file:REGS|regs[12][13], register_file:REGS|regs[13][13], ; +; ; ; register_file:REGS|regs[14][13], register_file:REGS|regs[15][13], ; +; ; ; register_file:REGS|regs[16][13], register_file:REGS|regs[17][13], ; +; ; ; register_file:REGS|regs[18][13], register_file:REGS|regs[19][13], ; +; ; ; register_file:REGS|regs[20][13], register_file:REGS|regs[21][13], ; +; ; ; register_file:REGS|regs[22][13], register_file:REGS|regs[23][13], ; +; ; ; register_file:REGS|regs[24][13], register_file:REGS|regs[25][13], ; +; ; ; register_file:REGS|regs[26][13], register_file:REGS|regs[27][13], ; +; ; ; register_file:REGS|regs[28][13], register_file:REGS|regs[29][13], ; +; ; ; register_file:REGS|regs[30][13], register_file:REGS|regs[31][13], ; +; ; ; register_file:REGS|regs[0][29], register_file:REGS|regs[1][29], ; +; ; ; register_file:REGS|regs[2][29], register_file:REGS|regs[3][29], ; +; ; ; register_file:REGS|regs[4][29], register_file:REGS|regs[5][29], ; +; ; ; register_file:REGS|regs[6][29], register_file:REGS|regs[7][29], ; +; ; ; register_file:REGS|regs[8][29], register_file:REGS|regs[9][29], ; +; ; ; register_file:REGS|regs[10][29], register_file:REGS|regs[11][29], ; +; ; ; register_file:REGS|regs[12][29], register_file:REGS|regs[13][29], ; +; ; ; register_file:REGS|regs[14][29], register_file:REGS|regs[15][29], ; +; ; ; register_file:REGS|regs[16][29], register_file:REGS|regs[17][29], ; +; ; ; register_file:REGS|regs[18][29], register_file:REGS|regs[19][29], ; +; ; ; register_file:REGS|regs[20][29], register_file:REGS|regs[21][29], ; +; ; ; register_file:REGS|regs[22][29], register_file:REGS|regs[23][29], ; +; ; ; register_file:REGS|regs[24][29], register_file:REGS|regs[25][29], ; +; ; ; register_file:REGS|regs[26][29], register_file:REGS|regs[27][29], ; +; ; ; register_file:REGS|regs[28][29], register_file:REGS|regs[29][29], ; +; ; ; register_file:REGS|regs[30][29], register_file:REGS|regs[31][29], ; +; ; ; register_file:REGS|regs[0][12], register_file:REGS|regs[1][12], ; +; ; ; register_file:REGS|regs[2][12], register_file:REGS|regs[3][12], ; +; ; ; register_file:REGS|regs[4][12], register_file:REGS|regs[5][12], ; +; ; ; register_file:REGS|regs[6][12], register_file:REGS|regs[7][12], ; +; ; ; register_file:REGS|regs[8][12], register_file:REGS|regs[9][12], ; +; ; ; register_file:REGS|regs[10][12], register_file:REGS|regs[11][12], ; +; ; ; register_file:REGS|regs[12][12], register_file:REGS|regs[13][12], ; +; ; ; register_file:REGS|regs[14][12], register_file:REGS|regs[15][12], ; +; ; ; register_file:REGS|regs[16][12], register_file:REGS|regs[17][12], ; +; ; ; register_file:REGS|regs[18][12], register_file:REGS|regs[19][12], ; +; ; ; register_file:REGS|regs[20][12], register_file:REGS|regs[21][12], ; +; ; ; register_file:REGS|regs[22][12], register_file:REGS|regs[23][12], ; +; ; ; register_file:REGS|regs[24][12], register_file:REGS|regs[25][12], ; +; ; ; register_file:REGS|regs[26][12], register_file:REGS|regs[27][12], ; +; ; ; register_file:REGS|regs[28][12], register_file:REGS|regs[29][12], ; +; ; ; register_file:REGS|regs[30][12], register_file:REGS|regs[31][12], ; +; ; ; register_file:REGS|regs[0][28], register_file:REGS|regs[1][28], ; +; ; ; register_file:REGS|regs[2][28], register_file:REGS|regs[3][28], ; +; ; ; register_file:REGS|regs[4][28], register_file:REGS|regs[5][28], ; +; ; ; register_file:REGS|regs[6][28], register_file:REGS|regs[7][28], ; +; ; ; register_file:REGS|regs[8][28], register_file:REGS|regs[9][28], ; +; ; ; register_file:REGS|regs[10][28], register_file:REGS|regs[11][28], ; +; ; ; register_file:REGS|regs[12][28], register_file:REGS|regs[13][28], ; +; ; ; register_file:REGS|regs[14][28], register_file:REGS|regs[15][28], ; +; ; ; register_file:REGS|regs[16][28], register_file:REGS|regs[17][28], ; +; ; ; register_file:REGS|regs[18][28], register_file:REGS|regs[19][28], ; +; ; ; register_file:REGS|regs[20][28], register_file:REGS|regs[21][28], ; +; ; ; register_file:REGS|regs[22][28], register_file:REGS|regs[23][28], ; +; ; ; register_file:REGS|regs[24][28], register_file:REGS|regs[25][28], ; +; ; ; register_file:REGS|regs[26][28], register_file:REGS|regs[27][28], ; +; ; ; register_file:REGS|regs[28][28], register_file:REGS|regs[29][28], ; +; ; ; register_file:REGS|regs[30][28], register_file:REGS|regs[31][28], ; +; ; ; register_file:REGS|regs[0][1], register_file:REGS|regs[16][1], ; +; ; ; register_file:REGS|regs[17][1], register_file:REGS|regs[18][1], ; +; ; ; register_file:REGS|regs[19][1], register_file:REGS|regs[20][1], ; +; ; ; register_file:REGS|regs[21][1], register_file:REGS|regs[22][1], ; +; ; ; register_file:REGS|regs[23][1], register_file:REGS|regs[24][1], ; +; ; ; register_file:REGS|regs[25][1], register_file:REGS|regs[26][1], ; +; ; ; register_file:REGS|regs[27][1], register_file:REGS|regs[28][1], ; +; ; ; register_file:REGS|regs[29][1], register_file:REGS|regs[30][1], ; +; ; ; register_file:REGS|regs[31][1], register_file:REGS|regs[0][0], ; +; ; ; register_file:REGS|regs[16][0], register_file:REGS|regs[17][0], ; +; ; ; register_file:REGS|regs[18][0], register_file:REGS|regs[19][0], ; +; ; ; register_file:REGS|regs[20][0], register_file:REGS|regs[21][0], ; +; ; ; register_file:REGS|regs[22][0], register_file:REGS|regs[23][0], ; +; ; ; register_file:REGS|regs[24][0], register_file:REGS|regs[25][0], ; +; ; ; register_file:REGS|regs[26][0], register_file:REGS|regs[27][0], ; +; ; ; register_file:REGS|regs[28][0], register_file:REGS|regs[29][0], ; +; ; ; register_file:REGS|regs[30][0], register_file:REGS|regs[31][0], ; +; ; ; register_file:REGS|regs[1][1], register_file:REGS|regs[2][1], ; +; ; ; register_file:REGS|regs[3][1], register_file:REGS|regs[15][1], ; +; ; ; register_file:REGS|regs[5][1], register_file:REGS|regs[6][1], ; +; ; ; register_file:REGS|regs[7][1], register_file:REGS|regs[11][1], ; +; ; ; register_file:REGS|regs[1][0], register_file:REGS|regs[2][0], ; +; ; ; register_file:REGS|regs[3][0], register_file:REGS|regs[15][0], ; +; ; ; register_file:REGS|regs[5][0], register_file:REGS|regs[6][0], ; +; ; ; register_file:REGS|regs[7][0], register_file:REGS|regs[11][0], ; +; ; ; register_file:REGS|regs[4][0], register_file:REGS|regs[12][0], ; +; ; ; register_file:REGS|regs[13][0], register_file:REGS|regs[14][0], ; +; ; ; register_file:REGS|regs[8][0], register_file:REGS|regs[9][0], ; +; ; ; register_file:REGS|regs[10][0], register_file:REGS|regs[4][1], ; +; ; ; register_file:REGS|regs[12][1], register_file:REGS|regs[13][1], ; +; ; ; register_file:REGS|regs[14][1], register_file:REGS|regs[8][1], ; +; ; ; register_file:REGS|regs[9][1], register_file:REGS|regs[10][1], ; +; ; ; instruction_counter:PC|pc[2], instruction_counter:PC|pc[3], ; +; ; ; instruction_counter:PC|pc[4], instruction_counter:PC|pc[5], ; +; ; ; instruction_counter:PC|pc[6], instruction_counter:PC|pc[7], ; +; ; ; instruction_counter:PC|pc[8], instruction_counter:PC|pc[9] ; ++------------------------------+--------------------------------+-------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+ +; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |assignment2|alu:ALU|Mux27 ; +; 8:1 ; 2 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |assignment2|register_file:REGS|Mux63 ; +; 7:1 ; 3 bits ; 12 LEs ; 9 LEs ; 3 LEs ; No ; |assignment2|alu:ALU|Mux26 ; +; 32:1 ; 2 bits ; 42 LEs ; 42 LEs ; 0 LEs ; No ; |assignment2|Mux30 ; +; 24:1 ; 2 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |assignment2|register_file:REGS|Mux31 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Top-level Entity: |assignment2 ; ++----------------+-------+----------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------+ +; width ; 5 ; Signed Integer ; +; ramsz ; 9 ; Signed Integer ; +; romsz ; 10 ; Signed Integer ; ++----------------+-------+----------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: instruction_counter:PC ; ++----------------+-------+--------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------+ +; width ; 5 ; Signed Integer ; ++----------------+-------+--------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------+ +; Parameter Settings for User Entity Instance: rom:ROM ; ++----------------+-------+-----------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------+ +; m ; 10 ; Signed Integer ; +; p ; 32 ; Signed Integer ; ++----------------+-------+-----------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------+ +; Parameter Settings for User Entity Instance: ram:RAM ; ++----------------+-------+-----------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------+ +; addrwidth ; 9 ; Signed Integer ; +; datawidth ; 32 ; Signed Integer ; ++----------------+-------+-----------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: register_file:REGS ; ++----------------+-------+----------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------+ +; width ; 5 ; Signed Integer ; +; nregs ; 5 ; Signed Integer ; ++----------------+-------+----------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: sign_extender:SIGNEXT ; ++----------------+-------+-------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------+ +; in_width ; 4 ; Signed Integer ; +; out_width ; 5 ; Signed Integer ; ++----------------+-------+-------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------+ +; Parameter Settings for User Entity Instance: alu:ALU ; ++----------------+-------+-----------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------+ +; width ; 5 ; Signed Integer ; ++----------------+-------+-----------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: alu:ALU|asu:adder_unit ; ++----------------+-------+--------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------+ +; width ; 5 ; Signed Integer ; ++----------------+-------+--------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: alu:ALU|lu:logic_unit ; ++----------------+-------+-------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------+ +; width ; 5 ; Signed Integer ; ++----------------+-------+-------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit3" ; ++---------+-------+----------+------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+------------------------------------------+ +; rbi_inv ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit2" ; ++---------+-------+----------+------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+------------------------------------------+ +; rbi_inv ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit1" ; ++---------+-------+----------+------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+------------------------------------------+ +; rbi_inv ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit0" ; ++---------+-------+----------+------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+------------------------------------------+ +; rbi_inv ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "alu:ALU" ; ++-------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ +; flags ; Output ; Warning ; Output or bidir port (3 bits) is wider than the port expression (2 bits) it drives; bit(s) "flags[2..2]" have no fanouts ; +; flags ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++-------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------+ +; Port Connectivity Checks: "sign_extender:SIGNEXT" ; ++------+-------+----------+-------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+-------------------------+ +; op ; Input ; Info ; Stuck at VCC ; ++------+-------+----------+-------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "control_unit:CONTROL_UNIT|instruction_classifier:CLASSIFIER" ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; F ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------+--------+----------+-------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "control_unit:CONTROL_UNIT" ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; B ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------+--------+----------+-------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "ram:RAM" ; ++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+ +; addr ; Input ; Warning ; Input port expression (32 bits) is smaller than the input port (512 bits) it drives. Extra input bit(s) "addr[511..32]" will be connected to GND. ; ++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "instruction_counter:PC" ; ++------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; we ; Input ; Info ; Stuck at GND ; +; W ; Input ; Warning ; Input port expression (10 bits) is smaller than the input port (32 bits) it drives. Extra input bit(s) "W[31..10]" will be connected to GND. ; +; addr ; Output ; Warning ; Output or bidir port (32 bits) is wider than the port expression (10 bits) it drives; bit(s) "addr[31..10]" have no fanouts ; ++------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; arriav_lcell_comb ; 1 ; +; normal ; 1 ; +; 0 data inputs ; 1 ; +; boundary_port ; 40 ; +; ; ; +; Max LUT depth ; 0.00 ; +; Average LUT depth ; 0.00 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Oct 15 15:04:10 2026 + Info: Processing started: Fri Oct 16 09:58:06 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 Info (20032): Parallel compilation is enabled and will use up to 2 processors Info (12021): Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv @@ -171,7 +6039,7 @@ Info (12021): Found 14 design units, including 14 entities, in source file /home Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4 Info (12023): Found entity 4: instruction_counter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv Line: 4 Info (12023): Found entity 5: instruction_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv Line: 3 - Info (12023): Found entity 6: instruction_module_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv Line: 4 + Info (12023): Found entity 6: control_unit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv Line: 5 Info (12023): Found entity 7: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4 Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3 Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9 @@ -179,29 +6047,86 @@ Info (12021): Found 14 design units, including 14 entities, in source file /home Info (12023): Found entity 11: sign_extender File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 4 Info (12023): Found entity 12: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv Line: 3 Info (12023): Found entity 13: seven_seg_4digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 5 - Info (12023): Found entity 14: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16 + Info (12023): Found entity 14: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15 Info (12127): Elaborating entity "assignment2" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at assignment2.sv(100): truncated value with size 32 to match size of target (10) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 100 -Warning (10030): Net "flags[2]" at assignment2.sv(55) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 55 -Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 62 -Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 64 +Warning (10230): Verilog HDL assignment warning at assignment2.sv(87): truncated value with size 32 to match size of target (10) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 87 +Warning (10030): Net "flags[2]" at assignment2.sv(48) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 48 +Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 55 +Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 57 Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16 Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 -Info (12128): Elaborating entity "ram" for hierarchy "ram:RAM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 67 -Warning (10230): Verilog HDL assignment warning at ram.sv(23): truncated value with size 32 to match size of target (8) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 23 -Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 69 -Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 76 -Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 85 +Info (12128): Elaborating entity "ram" for hierarchy "ram:RAM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 60 +Warning (10230): Verilog HDL assignment warning at ram.sv(18): truncated value with size 8 to match size of target (2) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 18 +Warning (10230): Verilog HDL assignment warning at ram.sv(24): truncated value with size 32 to match size of target (2) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 24 +Info (12128): Elaborating entity "control_unit" for hierarchy "control_unit:CONTROL_UNIT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 64 +Warning (10230): Verilog HDL assignment warning at control_unit.sv(29): truncated value with size 6 to match size of target (4) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv Line: 29 +Info (12128): Elaborating entity "instruction_classifier" for hierarchy "control_unit:CONTROL_UNIT|instruction_classifier:CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv Line: 23 +Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 73 Warning (10855): Verilog HDL warning at register_file.sv(14): initial value for variable regs should be constant File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 14 -Info (12128): Elaborating entity "sign_extender" for hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 88 -Error (10043): Verilog HDL unsupported feature error at sign_extender.sv(11): Procedural Continuous Assignment to register is not supported File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 11 -Error (12152): Can't elaborate user hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 88 -Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 8 warnings - Error: Peak virtual memory: 412 megabytes - Error: Processing ended: Thu Oct 15 15:04:21 2026 - Error: Elapsed time: 00:00:11 - Error: Total CPU time (on all processors): 00:00:24 +Info (12128): Elaborating entity "sign_extender" for hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 76 +Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 83 +Info (12128): Elaborating entity "asu" for hierarchy "alu:ALU|asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 18 +Info (12128): Elaborating entity "lu" for hierarchy "alu:ALU|lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 21 +Info (12128): Elaborating entity "seven_seg_4digit" for hierarchy "seven_seg_4digit:display" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 104 +Info (12128): Elaborating entity "seven_seg" for hierarchy "seven_seg_4digit:display|seven_seg:digit0" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 18 +Info (276014): Found 1 instances of uninferred RAM logic + Info (276007): RAM logic "ram:RAM|mem" is uninferred due to asynchronous read logic File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 13 +Warning (127007): Memory Initialization File or Hexadecimal (Intel-Format) File "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/db/assignment2.ram0_rom_d8639f5.hdl.mif" contains "don't care" values -- overwriting them with 0s +Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "out_seg_0[0]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_0[1]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_0[2]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_0[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_0[4]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_0[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_0[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_0[7]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_1[0]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Warning (13410): Pin "out_seg_1[1]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Warning (13410): Pin "out_seg_1[2]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Warning (13410): Pin "out_seg_1[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Warning (13410): Pin "out_seg_1[4]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Warning (13410): Pin "out_seg_1[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Warning (13410): Pin "out_seg_1[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Warning (13410): Pin "out_seg_1[7]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24 + Warning (13410): Pin "out_seg_2[0]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_2[1]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_2[2]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_2[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_2[4]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_2[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_2[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_2[7]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_3[0]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Warning (13410): Pin "out_seg_3[1]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Warning (13410): Pin "out_seg_3[2]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Warning (13410): Pin "out_seg_3[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Warning (13410): Pin "out_seg_3[4]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Warning (13410): Pin "out_seg_3[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Warning (13410): Pin "out_seg_3[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 + Warning (13410): Pin "out_seg_3[7]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 +Info (17049): 30 registers lost all their fanouts during netlist optimizations. +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 8 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "HID_PC[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 20 + Warning (15610): No output dependent on input pin "HID_Hi_Low[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Warning (15610): No output dependent on input pin "HID_Register[4]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19 + Warning (15610): No output dependent on input pin "HID_Register[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19 + Warning (15610): No output dependent on input pin "HID_Register[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19 + Warning (15610): No output dependent on input pin "HID_Register[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19 + Warning (15610): No output dependent on input pin "HID_Register[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19 + Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 18 +Info (21057): Implemented 40 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 8 input pins + Info (21059): Implemented 32 output pins +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 54 warnings + Info: Peak virtual memory: 440 megabytes + Info: Processing ended: Fri Oct 16 09:58:19 2026 + Info: Elapsed time: 00:00:13 + Info: Total CPU time (on all processors): 00:00:27 diff --git a/Quartus/A2/output_files/assignment2.map.summary b/Quartus/A2/output_files/assignment2.map.summary index bea4812..fe6cf78 100644 --- a/Quartus/A2/output_files/assignment2.map.summary +++ b/Quartus/A2/output_files/assignment2.map.summary @@ -1,12 +1,17 @@ -Analysis & Synthesis Status : Failed - Thu Oct 15 15:04:20 2026 +Analysis & Synthesis Status : Successful - Fri Oct 16 09:58:19 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : assignment2 Top-level Entity Name : assignment2 Family : Cyclone V -Logic utilization (in ALMs) : N/A until Partition Merge -Total registers : N/A until Partition Merge -Total pins : N/A until Partition Merge -Total virtual pins : N/A until Partition Merge -Total block memory bits : N/A until Partition Merge -Total PLLs : N/A until Partition Merge -Total DLLs : N/A until Partition Merge +Logic utilization (in ALMs) : N/A +Total registers : 0 +Total pins : 40 +Total virtual pins : 0 +Total block memory bits : 0 +Total DSP Blocks : 0 +Total HSSI RX PCSs : 0 +Total HSSI PMA RX Deserializers : 0 +Total HSSI TX PCSs : 0 +Total HSSI PMA TX Serializers : 0 +Total PLLs : 0 +Total DLLs : 0 diff --git a/Quartus/A2/output_files/assignment2.sof b/Quartus/A2/output_files/assignment2.sof index 2e245b4..1c789f8 100644 Binary files a/Quartus/A2/output_files/assignment2.sof and b/Quartus/A2/output_files/assignment2.sof differ diff --git a/Quartus/A2/output_files/assignment2.sta.rpt b/Quartus/A2/output_files/assignment2.sta.rpt index 40f363a..5ea7ae9 100644 --- a/Quartus/A2/output_files/assignment2.sta.rpt +++ b/Quartus/A2/output_files/assignment2.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for assignment2 -Tue Oct 13 16:48:19 2026 +Fri Oct 16 09:59:02 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -326,14 +326,14 @@ No synchronizer chains to report. +-----------------+--------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +-----------------+--------------+-----------------+-----------------+ -; clk[0] ; 1.2 V ; 960 ps ; 960 ps ; -; HID_Register[0] ; 1.2 V ; 960 ps ; 960 ps ; -; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ; -; HID_Register[2] ; 1.2 V ; 960 ps ; 960 ps ; -; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ; -; HID_Register[4] ; 1.2 V ; 960 ps ; 960 ps ; ; HID_PC[0] ; 1.2 V ; 960 ps ; 960 ps ; ; HID_Hi_Low[0] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[4] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[2] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[0] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ; +; clk[0] ; 1.2 V ; 960 ps ; 960 ps ; +-----------------+--------------+-----------------+-----------------+ @@ -535,7 +535,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 16:48:14 2026 + Info: Processing started: Fri Oct 16 09:58:57 2026 Info: Command: quartus_sta assignment2 -c assignment2 Info: qsta_default_script.tcl version: #1 Info (20032): Parallel compilation is enabled and will use up to 2 processors @@ -594,8 +594,8 @@ Info (332140): No Minimum Pulse Width paths to report Info (332101): Design is fully constrained for setup requirements Info (332101): Design is fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 761 megabytes - Info: Processing ended: Tue Oct 13 16:48:19 2026 + Info: Peak virtual memory: 765 megabytes + Info: Processing ended: Fri Oct 16 09:59:02 2026 Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A2/simulation/questa/assignment2.svo b/Quartus/A2/simulation/questa/assignment2.svo index 6e1640e..180cccc 100644 --- a/Quartus/A2/simulation/questa/assignment2.svo +++ b/Quartus/A2/simulation/questa/assignment2.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "10/13/2026 16:48:22" +// DATE "10/16/2026 09:59:05" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 @@ -48,14 +48,7 @@ output [7:0] out_seg_2; output [7:0] out_seg_3; // Design Ports Information -// clk[0] => Location: PIN_Y16, I/O Standard: 1.2 V, Current Strength: Default -// HID_Register[0] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default -// HID_Register[1] => Location: PIN_V10, I/O Standard: 1.2 V, Current Strength: Default -// HID_Register[2] => Location: PIN_AC10, I/O Standard: 1.2 V, Current Strength: Default -// HID_Register[3] => Location: PIN_Y11, I/O Standard: 1.2 V, Current Strength: Default -// HID_Register[4] => Location: PIN_AE19, I/O Standard: 1.2 V, Current Strength: Default // HID_PC[0] => Location: PIN_W11, I/O Standard: 1.2 V, Current Strength: Default -// HID_Hi_Low[0] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default // out_seg_0[0] => Location: PIN_J25, I/O Standard: 2.5 V, Current Strength: Default // out_seg_0[1] => Location: PIN_V19, I/O Standard: 1.2 V, Current Strength: Default // out_seg_0[2] => Location: PIN_V18, I/O Standard: 1.2 V, Current Strength: Default @@ -88,6 +81,13 @@ output [7:0] out_seg_3; // out_seg_3[5] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default // out_seg_3[6] => Location: PIN_AC23, I/O Standard: 2.5 V, Current Strength: Default // out_seg_3[7] => Location: PIN_AC22, I/O Standard: 2.5 V, Current Strength: Default +// HID_Hi_Low[0] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[4] => Location: PIN_AE19, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[2] => Location: PIN_AC10, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[0] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[1] => Location: PIN_V10, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[3] => Location: PIN_Y11, I/O Standard: 1.2 V, Current Strength: Default +// clk[0] => Location: PIN_Y16, I/O Standard: 1.2 V, Current Strength: Default wire gnd; @@ -101,20 +101,20 @@ assign unknown = 1'bx; tri1 devclrn; tri1 devpor; tri1 devoe; -wire \clk[0]~input_o ; -wire \HID_Register[0]~input_o ; -wire \HID_Register[1]~input_o ; -wire \HID_Register[2]~input_o ; -wire \HID_Register[3]~input_o ; -wire \HID_Register[4]~input_o ; wire \HID_PC[0]~input_o ; wire \HID_Hi_Low[0]~input_o ; +wire \HID_Register[4]~input_o ; +wire \HID_Register[2]~input_o ; +wire \HID_Register[0]~input_o ; +wire \HID_Register[1]~input_o ; +wire \HID_Register[3]~input_o ; +wire \clk[0]~input_o ; wire \~QUARTUS_CREATED_GND~I_combout ; // Location: IOOBUF_X68_Y32_N79 cyclonev_io_obuf \out_seg_0[0]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -130,7 +130,7 @@ defparam \out_seg_0[0]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X66_Y0_N2 cyclonev_io_obuf \out_seg_0[1]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -146,7 +146,7 @@ defparam \out_seg_0[1]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X64_Y0_N2 cyclonev_io_obuf \out_seg_0[2]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -178,7 +178,7 @@ defparam \out_seg_0[3]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X66_Y0_N19 cyclonev_io_obuf \out_seg_0[4]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -194,7 +194,7 @@ defparam \out_seg_0[4]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X65_Y0_N2 cyclonev_io_obuf \out_seg_0[5]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -226,7 +226,7 @@ defparam \out_seg_0[6]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X62_Y0_N42 cyclonev_io_obuf \out_seg_0[7]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -242,7 +242,7 @@ defparam \out_seg_0[7]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X17_Y61_N76 cyclonev_io_obuf \out_seg_1[0]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -274,7 +274,7 @@ defparam \out_seg_1[1]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X64_Y0_N36 cyclonev_io_obuf \out_seg_1[2]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -290,7 +290,7 @@ defparam \out_seg_1[2]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X65_Y0_N36 cyclonev_io_obuf \out_seg_1[3]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -338,7 +338,7 @@ defparam \out_seg_1[5]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X65_Y0_N53 cyclonev_io_obuf \out_seg_1[6]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -354,7 +354,7 @@ defparam \out_seg_1[6]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X62_Y0_N93 cyclonev_io_obuf \out_seg_1[7]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -370,7 +370,7 @@ defparam \out_seg_1[7]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X64_Y61_N2 cyclonev_io_obuf \out_seg_2[0]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -386,7 +386,7 @@ defparam \out_seg_2[0]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X7_Y0_N36 cyclonev_io_obuf \out_seg_2[1]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -402,7 +402,7 @@ defparam \out_seg_2[1]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X7_Y0_N53 cyclonev_io_obuf \out_seg_2[2]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -418,7 +418,7 @@ defparam \out_seg_2[2]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X68_Y13_N22 cyclonev_io_obuf \out_seg_2[3]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -434,7 +434,7 @@ defparam \out_seg_2[3]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X68_Y12_N5 cyclonev_io_obuf \out_seg_2[4]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -482,7 +482,7 @@ defparam \out_seg_2[6]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X68_Y11_N5 cyclonev_io_obuf \out_seg_2[7]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -498,7 +498,7 @@ defparam \out_seg_2[7]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X53_Y61_N2 cyclonev_io_obuf \out_seg_3[0]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -514,7 +514,7 @@ defparam \out_seg_3[0]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X68_Y13_N56 cyclonev_io_obuf \out_seg_3[1]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -562,7 +562,7 @@ defparam \out_seg_3[3]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X68_Y11_N39 cyclonev_io_obuf \out_seg_3[4]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -578,7 +578,7 @@ defparam \out_seg_3[4]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X68_Y12_N39 cyclonev_io_obuf \out_seg_3[5]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -594,7 +594,7 @@ defparam \out_seg_3[5]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X68_Y10_N96 cyclonev_io_obuf \out_seg_3[6]~output ( - .i(gnd), + .i(vcc), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -624,15 +624,48 @@ defparam \out_seg_3[7]~output .open_drain_output = "false"; defparam \out_seg_3[7]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOIBUF_X46_Y0_N18 -cyclonev_io_ibuf \clk[0]~input ( - .i(clk[0]), +// Location: IOIBUF_X10_Y0_N41 +cyclonev_io_ibuf \HID_PC[0]~input ( + .i(HID_PC[0]), .ibar(gnd), .dynamicterminationcontrol(gnd), - .o(\clk[0]~input_o )); + .o(\HID_PC[0]~input_o )); // synopsys translate_off -defparam \clk[0]~input .bus_hold = "false"; -defparam \clk[0]~input .simulate_z_as = "z"; +defparam \HID_PC[0]~input .bus_hold = "false"; +defparam \HID_PC[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N52 +cyclonev_io_ibuf \HID_Hi_Low[0]~input ( + .i(HID_Hi_Low[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_Hi_Low[0]~input_o )); +// synopsys translate_off +defparam \HID_Hi_Low[0]~input .bus_hold = "false"; +defparam \HID_Hi_Low[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X50_Y0_N35 +cyclonev_io_ibuf \HID_Register[4]~input ( + .i(HID_Register[4]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_Register[4]~input_o )); +// synopsys translate_off +defparam \HID_Register[4]~input .bus_hold = "false"; +defparam \HID_Register[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X12_Y0_N52 +cyclonev_io_ibuf \HID_Register[2]~input ( + .i(HID_Register[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_Register[2]~input_o )); +// synopsys translate_off +defparam \HID_Register[2]~input .bus_hold = "false"; +defparam \HID_Register[2]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X12_Y0_N35 @@ -657,17 +690,6 @@ defparam \HID_Register[1]~input .bus_hold = "false"; defparam \HID_Register[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: IOIBUF_X12_Y0_N52 -cyclonev_io_ibuf \HID_Register[2]~input ( - .i(HID_Register[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\HID_Register[2]~input_o )); -// synopsys translate_off -defparam \HID_Register[2]~input .bus_hold = "false"; -defparam \HID_Register[2]~input .simulate_z_as = "z"; -// synopsys translate_on - // Location: IOIBUF_X10_Y0_N58 cyclonev_io_ibuf \HID_Register[3]~input ( .i(HID_Register[3]), @@ -679,37 +701,15 @@ defparam \HID_Register[3]~input .bus_hold = "false"; defparam \HID_Register[3]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: IOIBUF_X50_Y0_N35 -cyclonev_io_ibuf \HID_Register[4]~input ( - .i(HID_Register[4]), +// Location: IOIBUF_X46_Y0_N18 +cyclonev_io_ibuf \clk[0]~input ( + .i(clk[0]), .ibar(gnd), .dynamicterminationcontrol(gnd), - .o(\HID_Register[4]~input_o )); + .o(\clk[0]~input_o )); // synopsys translate_off -defparam \HID_Register[4]~input .bus_hold = "false"; -defparam \HID_Register[4]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X10_Y0_N41 -cyclonev_io_ibuf \HID_PC[0]~input ( - .i(HID_PC[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\HID_PC[0]~input_o )); -// synopsys translate_off -defparam \HID_PC[0]~input .bus_hold = "false"; -defparam \HID_PC[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X14_Y0_N52 -cyclonev_io_ibuf \HID_Hi_Low[0]~input ( - .i(HID_Hi_Low[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\HID_Hi_Low[0]~input_o )); -// synopsys translate_off -defparam \HID_Hi_Low[0]~input .bus_hold = "false"; -defparam \HID_Hi_Low[0]~input .simulate_z_as = "z"; +defparam \clk[0]~input .bus_hold = "false"; +defparam \clk[0]~input .simulate_z_as = "z"; // synopsys translate_on // Location: LABCELL_X56_Y45_N3 diff --git a/modules/assignment2.sv b/modules/assignment2.sv index 36426c5..06bd084 100644 --- a/modules/assignment2.sv +++ b/modules/assignment2.sv @@ -12,7 +12,7 @@ `include "seven_seg_4digit.sv" -module assignment2 #(width=5, ramsz=9, romsz=10) ( +module assignment2 #(width=5, romsz=10) ( input logic [0:0] clk `ifdef QUARTUS_SYNTH , @@ -51,13 +51,17 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( logic [2**width-1:0] rd; logic [0:0] rd_we; logic [31:0] regs_out [32]; + + // ALU intermediates + logic [2**width-1:0] rd_alu; + logic [2**width-1:0] rt_alu; instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr); rom #(romsz, 2**width) ROM (pc_addr, instruction); logic [2**width-1:0] rd_mem; - ram #(ramsz, 2**width) RAM (clk, rd_alu, M2W, rt, rd_mem); + ram #(width) RAM (clk, rd_alu, M2W, rt, rd_mem); control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0], M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW @@ -78,8 +82,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( // - ALU srcB // - PCBranch (rel jump of 4-byte words) - logic [2**width-1:0] rd_alu; - logic [2**width-1:0] rt_alu; + alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]); assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt); diff --git a/modules/ram.sv b/modules/ram.sv index eaddf77..86cad81 100644 --- a/modules/ram.sv +++ b/modules/ram.sv @@ -1,21 +1,21 @@ `ifndef RAM_H `define RAM_H -module ram #(addrwidth=9, datawidth=5)( - input logic [0:0] clk, - input logic [2**addrwidth-1:0] addr, - input logic [0:0] we, - input logic [datawidth-1:0] data_in, - output logic [datawidth-1:0] data_out +module ram #(datawidth=5)( + input logic [0:0] clk, + input logic [2**datawidth-1:0] addr, + input logic [0:0] we, + input logic [datawidth-1:0] data_in, + output logic [datawidth-1:0] data_out ); // TODO: Make this byte-sized, NOT word-sized! - logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0]; + logic [2**datawidth-1:0] mem[0:255]; // NOTE: Possible issue with assignments still pending by end of initial block initial begin - for (integer ADDR = 0; ADDR < 2**(addrwidth+$clog2(datawidth)-3); ++ADDR) begin - mem[ADDR] <= 8'b0; + for (integer ADDR = 0; ADDR < 256); ADDR = ADDR + 1) begin + mem[ADDR] <= 32'b0; end end