TroubleElectrical/FPGA_Uni
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Updated RAM code to make sure Bus width is 32 bits

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TroubleElectrical committed 2026-10-16 11:32:47 +11:00
1 parent dca673b039
commit 5d9e7f541e
192 files changed
+15279 -3328
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Quartus/A2/output_files/assignment2.sta.rpt
+10 -10
View File
@@ -1,5 +1,5 @@
Timing Analyzer report for assignment2
Tue Oct 13 16:48:19 2026
Fri Oct 16 09:59:02 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -326,14 +326,14 @@ No synchronizer chains to report.
+-----------------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-----------------+--------------+-----------------+-----------------+
; clk[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[2] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[4] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_PC[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Hi_Low[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[4] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[2] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ;
; clk[0] ; 1.2 V ; 960 ps ; 960 ps ;
+-----------------+--------------+-----------------+-----------------+
@@ -535,7 +535,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:48:14 2026
Info: Processing started: Fri Oct 16 09:58:57 2026
Info: Command: quartus_sta assignment2 -c assignment2
Info: qsta_default_script.tcl version: #1
Info (20032): Parallel compilation is enabled and will use up to 2 processors
@@ -594,8 +594,8 @@ Info (332140): No Minimum Pulse Width paths to report
Info (332101): Design is fully constrained for setup requirements
Info (332101): Design is fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 761 megabytes
Info: Processing ended: Tue Oct 13 16:48:19 2026
Info: Peak virtual memory: 765 megabytes
Info: Processing ended: Fri Oct 16 09:59:02 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05