TroubleElectrical/FPGA_Uni
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Updated RAM code to make sure Bus width is 32 bits

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TroubleElectrical committed 2026-10-16 11:32:47 +11:00
1 parent dca673b039
commit 5d9e7f541e
192 files changed
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Quartus/A2/output_files/assignment2.map.summary
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Analysis & Synthesis Status : Failed - Thu Oct 15 15:04:20 2026
Analysis & Synthesis Status : Successful - Fri Oct 16 09:58:19 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Family : Cyclone V
Logic utilization (in ALMs) : N/A until Partition Merge
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total block memory bits : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 40
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0
Total DLLs : 0