TroubleElectrical/FPGA_Uni
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Updated RAM code to make sure Bus width is 32 bits

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TroubleElectrical committed 2026-10-16 11:32:47 +11:00
1 parent dca673b039
commit 5d9e7f541e
192 files changed
+15279 -3328
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Quartus/A2/output_files/assignment2.eda.rpt
+5 -5
View File
@@ -1,5 +1,5 @@
EDA Netlist Writer report for assignment2
Tue Oct 13 16:48:22 2026
Fri Oct 16 09:59:05 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:48:22 2026 ;
; EDA Netlist Writer Status ; Successful - Fri Oct 16 09:59:05 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
@@ -81,12 +81,12 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:48:21 2026
Info: Processing started: Fri Oct 16 09:59:04 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 670 megabytes
Info: Processing ended: Tue Oct 13 16:48:22 2026
Info: Peak virtual memory: 669 megabytes
Info: Processing ended: Fri Oct 16 09:59:05 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01