TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Updated RAM code to make sure Bus width is 32 bits

Browse Source
This commit is contained in:
TroubleElectrical committed 2026-10-16 11:32:47 +11:00
1 parent dca673b039
commit 5d9e7f541e
192 files changed
+15279 -3328
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Quartus/A2/output_files/assignment2.asm.rpt
+7 -7
View File
@@ -1,5 +1,5 @@
Assembler report for assignment2
Tue Oct 13 16:48:13 2026
Fri Oct 16 09:58:56 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Oct 13 16:48:13 2026 ;
; Assembler Status ; Successful - Fri Oct 16 09:58:56 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
+----------------+--------------------------+
; Option ; Setting ;
+----------------+--------------------------+
; JTAG usercode ; 0x00780D54 ;
; Checksum ; 0x00780D54 ;
; JTAG usercode ; 0x00780AC3 ;
; Checksum ; 0x00780AC3 ;
+----------------+--------------------------+
@@ -78,12 +78,12 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:48:07 2026
Info: Processing started: Fri Oct 16 09:58:50 2026
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 516 megabytes
Info: Processing ended: Tue Oct 13 16:48:13 2026
Info: Peak virtual memory: 520 megabytes
Info: Processing ended: Fri Oct 16 09:58:56 2026
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05
Quartus/A2/output_files/assignment2.done
+1 -1
View File
@@ -1 +1 @@
Tue Oct 13 16:48:22 2026
Fri Oct 16 09:59:05 2026
Quartus/A2/output_files/assignment2.drc.rpt
+194
View File
@@ -0,0 +1,194 @@
Design Assistant report for assignment2
Thu Oct 15 15:37:35 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Design Assistant Summary
3. Design Assistant Settings
4. Information only Violations
5. Design Assistant Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+-------------------------------------------------------------------------+
; Design Assistant Summary ;
+-----------------------------------+-------------------------------------+
; Design Assistant Status ; Analyzed - Thu Oct 15 15:37:35 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Total Critical Violations ; 0 ;
; Total High Violations ; 0 ;
; Total Medium Violations ; 0 ;
; Total Information only Violations ; 40 ;
; - Rule T102 ; 40 ;
+-----------------------------------+-------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Option ; Setting ; To ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Design Assistant mode ; Post-Fitting ; ;
; Threshold value for clock net not mapped to clock spines rule ; 25 ; ;
; Minimum number of clock port feed by gated clocks ; 30 ; ;
; Minimum number of node fan-out ; 30 ; ;
; Maximum number of nodes to report ; 50 ; ;
; Rule C101: Gated clock should be implemented according to the Intel FPGA standard scheme ; On ; ;
; Rule C102: Logic cell should not be used to generate an inverted clock signal ; On ; ;
; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; On ; ;
; Rule C104: Clock signal source should drive only clock input ports ; On ; ;
; Rule C105: Clock signal should be a global signal ; On ; ;
; Rule C106: Clock signal source should not drive registers triggered by different clock edges ; On ; ;
; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ;
; Rule R102: External reset signals should be synchronized using two cascaded registers ; On ; ;
; Rule R103: External reset signal should be correctly synchronized ; On ; ;
; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized ; On ; ;
; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized ; On ; ;
; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ;
; Rule T102: Top nodes with the highest number of fan-outs ; On ; ;
; Rule A101: Design should not contain combinational loops ; On ; ;
; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ;
; Rule A103: Design should not contain delay chains ; On ; ;
; Rule A104: Design should not contain ripple clock structures ; On ; ;
; Rule A105: Pulses should not be implemented asynchronously ; On ; ;
; Rule A106: Multiple pulses should not be generated in design ; On ; ;
; Rule A107: Design should not contain SR latches ; On ; ;
; Rule A108: Design should not contain latches ; On ; ;
; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ;
; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source ; On ; ;
; Rule S104: Clock port and any other port of a register should not be driven by the same signal source ; On ; ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
+------------------------------------------------------------------------------------------+
; Information only Violations ;
+----------------------------------------------------------+---------------------+---------+
; Rule name ; Name ; Fan-Out ;
+----------------------------------------------------------+---------------------+---------+
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[6]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[4]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[7]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[3]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[1]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[2]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[2]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[3]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[4]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[1]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[5]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[0]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[0]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_1[7]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[0]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[7]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[1]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[2]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[6]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[3]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[4]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_2[5]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[3] ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; HID_PC[0] ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; HID_Hi_Low[0] ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[4] ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[0]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[7]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[1]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[6]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[2]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[6]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[3]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[2] ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[4]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[1] ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_3[5]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; out_seg_0[5]~output ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; HID_Register[0] ; 1 ;
; Rule T102: Top nodes with the highest number of fan-outs ; clk[0] ; 1 ;
+----------------------------------------------------------+---------------------+---------+
+---------------------------+
; Design Assistant Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Design Assistant
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Thu Oct 15 15:37:34 2026
Info: Command: quartus_drc assignment2 -c assignment2
Critical Warning (332012): Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (308044): (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 40 node(s) with highest fan-out.
Info (308011): Node "out_seg_1[6]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24
Info (308011): Node "out_seg_3[4]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28
Info (308011): Node "out_seg_0[7]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
Info (308011): Node "out_seg_3[3]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28
Info (308011): Node "out_seg_1[1]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24
Info (308011): Node "out_seg_1[2]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24
Info (308011): Node "out_seg_3[2]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28
Info (308011): Node "out_seg_1[3]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24
Info (308011): Node "out_seg_1[4]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24
Info (308011): Node "out_seg_3[1]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28
Info (308011): Node "out_seg_1[5]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24
Info (308011): Node "out_seg_1[0]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24
Info (308011): Node "out_seg_3[0]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28
Info (308011): Node "out_seg_1[7]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 24
Info (308011): Node "out_seg_2[0]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
Info (308011): Node "out_seg_2[7]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
Info (308011): Node "out_seg_2[1]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
Info (308011): Node "out_seg_2[2]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
Info (308011): Node "out_seg_2[6]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
Info (308011): Node "out_seg_2[3]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
Info (308011): Node "out_seg_2[4]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
Info (308011): Node "out_seg_2[5]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
Info (308011): Node "HID_Register[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19
Info (308011): Node "HID_PC[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 20
Info (308011): Node "HID_Hi_Low[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
Info (308011): Node "HID_Register[4]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19
Info (308011): Node "out_seg_0[0]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
Info (308011): Node "out_seg_3[7]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28
Info (308011): Node "out_seg_0[1]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
Info (308011): Node "out_seg_0[6]~output" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info (308007): Design Assistant information: finished post-fitting analysis of current design -- generated 40 information messages and 0 warning messages
Info: Quartus Prime Design Assistant was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 646 megabytes
Info: Processing ended: Thu Oct 15 15:37:35 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Quartus/A2/output_files/assignment2.eda.rpt
+5 -5
View File
@@ -1,5 +1,5 @@
EDA Netlist Writer report for assignment2
Tue Oct 13 16:48:22 2026
Fri Oct 16 09:59:05 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:48:22 2026 ;
; EDA Netlist Writer Status ; Successful - Fri Oct 16 09:59:05 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
@@ -81,12 +81,12 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:48:21 2026
Info: Processing started: Fri Oct 16 09:59:04 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 670 megabytes
Info: Processing ended: Tue Oct 13 16:48:22 2026
Info: Peak virtual memory: 669 megabytes
Info: Processing ended: Fri Oct 16 09:59:05 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Quartus/A2/output_files/assignment2.fit.rpt
+25 -25
View File
@@ -1,5 +1,5 @@
Fitter report for assignment2
Tue Oct 13 16:48:05 2026
Fri Oct 16 09:58:48 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -58,7 +58,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Tue Oct 13 16:48:05 2026 ;
; Fitter Status ; Successful - Fri Oct 16 09:58:48 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
@@ -1190,14 +1190,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
+-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
; clk[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_PC[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Hi_Low[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; out_seg_0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
@@ -1230,6 +1223,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; out_seg_3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_3[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; HID_Hi_Low[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; HID_Register[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; clk[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
@@ -1238,14 +1238,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; clk[0] ; ; ;
; HID_Register[0] ; ; ;
; HID_Register[1] ; ; ;
; HID_Register[2] ; ; ;
; HID_Register[3] ; ; ;
; HID_Register[4] ; ; ;
; HID_PC[0] ; ; ;
; HID_Hi_Low[0] ; ; ;
; HID_Register[4] ; ; ;
; HID_Register[2] ; ; ;
; HID_Register[0] ; ; ;
; HID_Register[1] ; ; ;
; HID_Register[3] ; ; ;
; clk[0] ; ; ;
+---------------------+-------------------+---------+
@@ -1334,14 +1334,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Inapplicable ; 40 ; 4 ; 4 ; 40 ; 40 ; 0 ; 4 ; 40 ; 40 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 0 ; 0 ; 40 ;
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; clk[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_PC[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Hi_Low[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_0[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
@@ -1374,6 +1367,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; out_seg_3[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_3[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_3[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Hi_Low[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; HID_Register[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; clk[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
@@ -1465,9 +1465,9 @@ Info (334004): Delay annotation completed successfully
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 1328 megabytes
Info: Processing ended: Tue Oct 13 16:48:06 2026
Info: Elapsed time: 00:00:28
Info: Peak virtual memory: 1336 megabytes
Info: Processing ended: Fri Oct 16 09:58:49 2026
Info: Elapsed time: 00:00:29
Info: Total CPU time (on all processors): 00:00:39
Quartus/A2/output_files/assignment2.fit.summary
+1 -1
View File
@@ -1,4 +1,4 @@
Fitter Status : Successful - Tue Oct 13 16:48:05 2026
Fitter Status : Successful - Fri Oct 16 09:58:48 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Quartus/A2/output_files/assignment2.flow.rpt
+40 -23
View File
@@ -1,5 +1,5 @@
Flow report for assignment2
Thu Oct 15 15:04:20 2026
Fri Oct 16 09:59:05 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -38,24 +38,29 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------------+-------------------------------------------------+
; Flow Status ; Flow Failed - Thu Oct 15 15:04:20 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total block memory bits ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+-------------------------------------------------+
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Fri Oct 16 09:59:05 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 40 / 364 ( 11 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ;
; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ;
; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ;
; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ;
; Total PLLs ; 0 / 12 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+-------------------------------------------------+
+-----------------------------------------+
@@ -63,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/15/2026 15:04:10 ;
; Start date & time ; 10/16/2026 09:58:06 ;
; Main task ; Compilation ;
; Revision Name ; assignment2 ;
+-------------------+---------------------+
@@ -74,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 268883478169649.179203705005251 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 231344018423319.179210508627966 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -98,8 +103,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 412 MB ; 00:00:24 ;
; Total ; 00:00:10 ; -- ; -- ; 00:00:24 ;
; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 427 MB ; 00:00:26 ;
; Fitter ; 00:00:28 ; 1.0 ; 1336 MB ; 00:00:38 ;
; Assembler ; 00:00:06 ; 1.0 ; 520 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 765 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 669 MB ; 00:00:01 ;
; Total ; 00:00:52 ; -- ; -- ; 00:01:15 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
@@ -109,6 +118,10 @@ on the Quartus Prime software download page.
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+---------------------+------------+------------+----------------+
; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; Fitter ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; Assembler ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; Timing Analyzer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; EDA Netlist Writer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
+----------------------+---------------------+------------+------------+----------------+
@@ -116,6 +129,10 @@ on the Quartus Prime software download page.
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
quartus_fit --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
quartus_sta assignment2 -c assignment2
quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Quartus/A2/output_files/assignment2.map.rpt
+5963 -38
View File
File diff suppressed because it is too large. Load diff
Quartus/A2/output_files/assignment2.map.summary
+13 -8
View File
@@ -1,12 +1,17 @@
Analysis & Synthesis Status : Failed - Thu Oct 15 15:04:20 2026
Analysis & Synthesis Status : Successful - Fri Oct 16 09:58:19 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Family : Cyclone V
Logic utilization (in ALMs) : N/A until Partition Merge
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total block memory bits : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 40
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0
Total DLLs : 0
Quartus/A2/output_files/assignment2.sof
BIN
View File
Binary file not shown.
Quartus/A2/output_files/assignment2.sta.rpt
+10 -10
View File
@@ -1,5 +1,5 @@
Timing Analyzer report for assignment2
Tue Oct 13 16:48:19 2026
Fri Oct 16 09:59:02 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -326,14 +326,14 @@ No synchronizer chains to report.
+-----------------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-----------------+--------------+-----------------+-----------------+
; clk[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[2] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[4] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_PC[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Hi_Low[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[4] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[2] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ;
; clk[0] ; 1.2 V ; 960 ps ; 960 ps ;
+-----------------+--------------+-----------------+-----------------+
@@ -535,7 +535,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 16:48:14 2026
Info: Processing started: Fri Oct 16 09:58:57 2026
Info: Command: quartus_sta assignment2 -c assignment2
Info: qsta_default_script.tcl version: #1
Info (20032): Parallel compilation is enabled and will use up to 2 processors
@@ -594,8 +594,8 @@ Info (332140): No Minimum Pulse Width paths to report
Info (332101): Design is fully constrained for setup requirements
Info (332101): Design is fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 761 megabytes
Info: Processing ended: Tue Oct 13 16:48:19 2026
Info: Peak virtual memory: 765 megabytes
Info: Processing ended: Fri Oct 16 09:59:02 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05