TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Updated RAM code to make sure Bus width is 32 bits

Browse Source
This commit is contained in:
TroubleElectrical committed 2026-10-16 11:32:47 +11:00
1 parent dca673b039
commit 5d9e7f541e
192 files changed
+15279 -3328
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Quartus/A2/db/assignment2.drc.qmsg
+12
View File
@@ -0,0 +1,12 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792039054929 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Design Assistant Quartus Prime " "Running Quartus Prime Design Assistant" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792039054929 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 15 15:37:34 2026 " "Processing started: Thu Oct 15 15:37:34 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792039054929 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Assistant" 0 -1 1792039054929 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_drc assignment2 -c assignment2 " "Command: quartus_drc assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Design Assistant" 0 -1 1792039054929 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Design Assistant" 0 -1 1792039055709 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Design Assistant" 0 -1 1792039055710 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Design Assistant" 0 -1 1792039055710 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Design Assistant" 0 -1 1792039055710 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Design Assistant" 0 -1 1792039055712 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Design Assistant" 0 -1 1792039055712 ""}
{ "Info" "IDRC_TOP_FANOUT" "Rule T102: Top nodes with the highest number of fan-outs 50 40 " "(Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 40 node(s) with highest fan-out." { { "Info" "IDRC_NODES_INFO" " out_seg_1\[6\]~output " "Node \"out_seg_1\[6\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 89 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_3\[4\]~output " "Node \"out_seg_3\[4\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 103 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_0\[7\]~output " "Node \"out_seg_0\[7\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 82 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_3\[3\]~output " "Node \"out_seg_3\[3\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 102 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_1\[1\]~output " "Node \"out_seg_1\[1\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_1\[2\]~output " "Node \"out_seg_1\[2\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 85 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_3\[2\]~output " "Node \"out_seg_3\[2\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 101 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_1\[3\]~output " "Node \"out_seg_1\[3\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 86 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_1\[4\]~output " "Node \"out_seg_1\[4\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 87 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_3\[1\]~output " "Node \"out_seg_3\[1\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 100 14177 15141 0 0 "" 0 "" "" } } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Design Software" 0 -1 1792039055724 ""} { "Info" "IDRC_NODES_INFO" " out_seg_1\[5\]~output " "Node \"out_seg_1\[5\]~output\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 88 14177 15141 0 0 "" 0 "" "" } } Line truncated
{ "Info" "IDRC_REPORT_HEALTH_POST_FITTER" "40 0 " "Design Assistant information: finished post-fitting analysis of current design -- generated 40 information messages and 0 warning messages" { } { } 2 308007 "Design Assistant information: finished post-fitting analysis of current design -- generated %1!d! information messages and %2!d! warning messages" 0 0 "Design Assistant" 0 -1 1792039055726 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Design Assistant 0 s 2 s Quartus Prime " "Quartus Prime Design Assistant was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "646 " "Peak virtual memory: 646 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792039055755 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 15 15:37:35 2026 " "Processing ended: Thu Oct 15 15:37:35 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792039055755 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792039055755 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792039055755 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Assistant" 0 -1 1792039055755 ""}