Updated RAM code to make sure Bus width is 32 bits

This commit is contained in:
TroubleElectrical committed 2026-10-16 11:32:47 +11:00
1 parent dca673b039
commit 5d9e7f541e
192 files changed
+15279 -3328

No files matched your search

+353 -102
View File
@@ -11,32 +11,32 @@ cModel Technology
d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
valu
Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
Z1 !s110 1789448641
Z1 !s110 1792107153
!i10b 1
!s100 Kh9ZlG?nRa:nnklUM3MaM0
!s100 meV@F]8El[fjh_ULLA@iR2
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
IlI`[:Ol82B@F8AM_FVkV41
I<0ZXcWH[]FIo]cjVef19`2
Z3 VDg1SIo80bB@j0V0VzS_@n1
S1
Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
Z5 w1789355084
w1792036226
8alu.sv
Falu.sv
!i122 18
L0 9 28
Z6 OV;L;2020.1;71
!i122 90
L0 9 31
Z5 OV;L;2020.1;71
r1
!s85 0
31
Z7 !s108 1789448641.000000
Z8 !s107 lu.sv|asu.sv|alu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
Z6 !s108 1792107152.000000
Z7 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
Z8 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
!i113 1
Z10 o-work work -sv
Z11 tCvgOpt 0
Z9 o-work work -sv
Z10 tCvgOpt 0
valu_tb
R0
R1
Z11 !s110 1792107152
!i10b 1
!s100 8=>8o`KV]hRM]V8AV?S[C1
R2
@@ -44,74 +44,150 @@ Iz[VXe9HJ@koSDFNR185;i1
R3
S1
R4
R5
Z12 w1789355084
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
!i122 18
!i122 79
L0 3 214
R6
R5
r1
!s85 0
31
R6
!s107 lu.sv|asu.sv|alu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
!i113 1
R9
R10
vassignment2
R0
R1
!i10b 1
!s100 GJCIM_l8Wa[9;0<RIgA[E0
R2
I7i7cEGK6dmN[?gYSA`MeR3
R3
S1
R4
w1792106709
8assignment2.sv
Fassignment2.sv
!i122 90
L0 15 91
R5
r1
!s85 0
31
R6
R7
R8
R9
!i113 1
R9
R10
R11
vasu
R0
R1
!i10b 1
!s100 MiS^hmH6XEfHgJYg=7c;32
!s100 P^h>QhJiM30V7KUMaaQ[k3
R2
I<<aDiX=d[PVLMK[L<GAWJ3
IzBgUoHUOOfMj??ZL^0FOM3
R3
S1
R4
R5
w1790228118
8asu.sv
Fasu.sv
!i122 18
L0 4 18
R6
!i122 90
L0 4 21
R5
r1
!s85 0
31
R6
R7
R8
R9
!i113 1
R9
R10
R11
vasu_tb
R0
!s110 1789448473
R11
!i10b 1
!s100 6Mz=>S]N8CcV@e24ZMO?A3
!s100 ?AMT1ejDgW=83T_P=nh4G1
R2
INFK7`kK]UQzEBD`:U7gC70
IcS>Hk9oO:RGFmfdUY9[i90
R3
S1
R4
Z12 w1788926090
Z13 w1789513270
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
!i122 16
!i122 82
L0 3 120
R6
R5
r1
!s85 0
31
!s108 1789448473.000000
R6
!s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
!i113 1
R9
R10
vByteIM
R0
R11
!i10b 1
!s100 ]V5Di195@?V=P`Y?PM;U=0
R2
Ie:hP;^zFCE^LSAOVoDF6C3
R3
S1
R4
w1792106811
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
!i122 83
L0 3 12
R5
r1
!s85 0
31
R6
!s107 rom.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
!i113 1
R9
R10
n@byte@i@m
vcontrol_unit
R0
R1
!i10b 1
!s100 8=J_D2S47^DbodSznO_Zc3
R2
ICLPRW`?<4jEk;O<a<:JfD1
R3
S1
R4
w1792040117
8control_unit.sv
Fcontrol_unit.sv
!i122 90
L0 5 31
R5
r1
!s85 0
31
R6
R7
R8
!i113 1
R9
R10
vinstruction_classifier
R0
Z13 !s110 1789448904
R1
!i10b 1
!s100 LBO=Ba0m3b@J?;=_fd^7P3
R2
@@ -119,24 +195,24 @@ I[MC9A^:kRAc`nk8<MdaKg2
R3
S1
R4
R5
Z14 w1790228042
8instruction_classifier.sv
Finstruction_classifier.sv
!i122 22
!i122 90
L0 3 18
R6
R5
r1
!s85 0
31
Z14 !s108 1789448904.000000
Z15 !s107 instruction_classifier.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv|
Z16 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv|
R6
R7
R8
!i113 1
R9
R10
R11
vinstruction_classifier_tb
R0
R13
R11
!i10b 1
!s100 UcoUK1il@9RM[8`l`mYQh2
R2
@@ -144,24 +220,49 @@ I;:>eJ6i8o;@kY_?aVJn:d3
R3
S1
R4
R5
R12
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
!i122 22
!i122 86
L0 2 51
R6
R5
r1
!s85 0
31
R14
R15
R16
R6
!s107 instruction_classifier.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv|
!i113 1
R9
R10
vinstruction_counter
R0
R1
!i10b 1
!s100 Gl3QY26LJ15Q7EONh4SzK3
R2
I1hlbD0fJDW[G]0]A8ceHA0
R3
S1
R4
w1791854498
8instruction_counter.sv
Finstruction_counter.sv
!i122 90
L0 4 17
R5
r1
!s85 0
31
R6
R7
R8
!i113 1
R9
R10
R11
vlu
R0
Z17 !s110 1789449208
R1
!i10b 1
!s100 H5AG9eSQKJkS4F`0;5hWl0
R2
@@ -169,24 +270,24 @@ IObN^<8?MCaP;K@UKCVaP^1
R3
S1
R4
R5
R14
8lu.sv
Flu.sv
!i122 26
Z18 L0 3 16
R6
!i122 90
Z15 L0 3 16
R5
r1
!s85 0
31
Z19 !s108 1789449208.000000
!s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
R6
R7
R8
!i113 1
R9
R10
R11
vlu_tb
R0
R17
R11
!i10b 1
!s100 AE_liX6DCD[3>b;K6Wgf72
R2
@@ -194,24 +295,124 @@ IC?h=m;SY77_D:GA0FR<P^2
R3
S1
R4
R12
w1788926090
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
!i122 26
!i122 89
L0 3 58
R6
R5
r1
!s85 0
31
R19
Z21 !s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
R20
R6
!s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
!i113 1
R9
R10
vmips_tb
R0
R1
!i10b 1
!s100 [;3LLg]jz>CL@TZ0g[C5g2
R2
ImO]Pc4zj;o69UAilj_VEd3
R3
S1
R4
w1792104861
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
!i122 90
L0 14 82
R5
r1
!s85 0
31
R6
R7
R8
!i113 1
R9
R10
vram
R0
R1
!i10b 1
!s100 a80AX>=1K`e^Xe^?2?j331
R2
I9H<bBYRWPh>SjRizgnUC41
R3
S1
R4
w1792039197
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
!i122 91
L0 4 26
R5
r1
!s85 0
31
Z16 !s108 1792107153.000000
!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv|
!i113 1
R9
R10
vregister_file
R0
R1
!i10b 1
!s100 FhA1A;hJHXYBBj3k;<@TW0
R2
I7[zSLUT47VibC4BZ`m8FC1
R3
S1
R4
w1792035553
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
!i122 92
L0 4 24
R5
r1
!s85 0
31
R16
!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv|
!i113 1
R9
R10
vrom
R0
R1
!i10b 1
!s100 WU3`[b3K8gX:gOXzLkih[1
R2
INYZO14fR4zIzAHU<HO=jM1
R3
S1
R4
w1792107144
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
!i122 93
L0 4 18
R5
r1
!s85 0
31
R16
!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv|
!i113 1
R9
R10
R11
vseven_seg
R0
Z22 !s110 1789449021
R1
!i10b 1
!s100 ^3LXNA>i`]oD>7BNB:Rd?3
R2
@@ -219,24 +420,49 @@ IedFU7?nB5ZOibY?bC8=L41
R3
S1
R4
R5
R14
8seven_seg.sv
Fseven_seg.sv
!i122 24
!i122 96
L0 3 23
R6
R5
r1
!s85 0
31
Z23 !s108 1789449021.000000
Z24 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
Z25 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
R16
Z17 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
Z18 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
!i113 1
R9
R10
vseven_seg_4digit
R0
R1
!i10b 1
!s100 MRn_YTIW^S4cR39n=0RMi0
R2
IYaD1MHdmne1KMOgV5M^f70
R3
S1
R4
w1791866874
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
!i122 95
L0 5 37
R5
r1
!s85 0
31
R16
!s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv|
!i113 1
R9
R10
R11
vseven_seg_tb
R0
R22
R1
!i10b 1
!s100 jPijM2]zTRBV8TFdD?Q`I1
R2
@@ -247,65 +473,90 @@ R4
w1788418794
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
!i122 24
!i122 96
L0 3 66
R6
R5
r1
!s85 0
31
R23
R24
R25
R16
R17
R18
!i113 1
R9
R10
R11
vshifter
R0
Z26 !s110 1789448794
R1
!i10b 1
!s100 <fMP57@WI80oPG2Je:5ab2
!s100 D0hzGhEI<?_?ELZe:f<RS1
R2
IX2;A_nH1:dH8`jIjb?8m:1
IzJzhQo`olGLa0f4lM55A42
R3
S1
R4
R5
R14
8shifter.sv
Fshifter.sv
!i122 20
R18
R6
!i122 98
R15
R5
r1
!s85 0
31
Z27 !s108 1789448794.000000
Z28 !s107 shifter.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
Z29 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
R16
Z19 !s107 shifter.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
!i113 1
R9
R10
R11
vshifter_tb
R0
R26
R1
!i10b 1
!s100 B34`X2Q:D=<a_YU@D_zb`0
!s100 TiConQ4:_WTd:PLNNG`Po3
R2
IP0?XY582]2;G`Y8WME:7Q2
Ia6ohf92lD=P<P]lDi667i2
R3
S1
R4
R12
R13
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
!i122 20
!i122 98
L0 2 76
R6
R5
r1
!s85 0
31
R27
R28
R29
R16
R19
R20
!i113 1
R9
R10
vsign_extender
R0
R1
!i10b 1
!s100 aKV[]M4PV<7m9ohWC7JSA0
R2
I6?e[:9@XB<KdO1NP<2VSz0
R3
S1
R4
w1792038654
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
!i122 99
L0 4 13
R5
r1
!s85 0
31
R16
!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv|
!i113 1
R9
R10
R11
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.