Updated RAM code to make sure Bus width is 32 bits

ModelSim/assignment2.sv

@@ -13,9 +13,7 @@
 
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (
-	input logic [0:0] clk
-`ifdef QUARTUS_SYNTH
-    ,
+	input logic [0:0] clk,
 	input logic [4:0] HID_Register,
 	input logic [0:0] HID_PC,
 	input logic [0:0] HID_Hi_Low,
@@ -24,7 +22,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	output logic[7:0] out_seg_1,
 	output logic[7:0] out_seg_2,
 	output logic[7:0] out_seg_3
-`endif
 	);
 	// Intermediate for displaying high / low of PC or Register
 	logic[15:0] PC_Reg_Display;
@@ -51,6 +48,10 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] rd;
 	logic [0:0] rd_we;
 	logic [31:0] regs_out [32];
+
+    // ALU intermeduates
+	logic [2**width-1:0] rd_alu;
+	logic [2**width-1:0] rt_alu;
 	
 	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
 	
@@ -78,8 +79,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
     //  - ALU srcB
     //  - PCBranch (rel jump of 4-byte words)
 
-	logic [2**width-1:0] rd_alu;
-	logic [2**width-1:0] rt_alu;
 	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
     assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);