TroubleElectrical/FPGA_Uni
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Updated RAM code to make sure Bus width is 32 bits

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TroubleElectrical committed 2026-10-16 11:32:47 +11:00
1 parent dca673b039
commit 5d9e7f541e
192 files changed
+15279 -3328
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ModelSim/Assignment_1_Q2.cr.mti
+1 -8
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@@ -1,11 +1,4 @@
/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module lu
Top level modules:
lu
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module lu
-- Compiling module lu_tb