Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni

modules/ByteIM.sv

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+`include "rom.sv"
+
+module ByteIM #(parameter m=5,n=2) (
+    input logic [m-1:0] Ad,
+    output logic [(2**n)*8-1:0] Dout );
+
+    // 2**n byte wide words
+    // m bit wide byte address
+    // 2**m bytes of memory
+    // 2**(m-n) memory words
+    // 2**(n+3) bit wide words
+    // Reads the whole word that contains the addressed byte
+    ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
+endmodule

modules/rom.sv

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+
+module ROM #(parameter m=7,p=4) (
+        input logic [m-1:0] Ad,
+        output logic [p-1:0] Dout
+    );
+    
+    logic [p-1:0] mem[2**m-1:0];
+    assign Dout = mem[Ad];
+
+    //Load the program in memory
+    // The machine code stored in text file program.dat written in Hex format
+    initial begin
+        $readmemh("program.dat",mem); //$readmemb for binary
+    end
+endmodule // end ROM module