Fixed a couple bugs introduced from merge-conflict resolution

modules/ram.sv

@@ -14,7 +14,7 @@ module ram #(addrwidth=9, datawidth=5)(
 
     // NOTE: Possible issue with assignments still pending by end of initial block
     initial begin
-        for (integer ADDR = 0; ADDR < 256); ADDR = ADDR + 1) begin
+        for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
             mem[ADDR] <= 32'b0;
         end
     end