diff --git a/modules/assignment2.sv b/modules/assignment2.sv
index d8e5d3c..9ea32f0 100644
--- a/modules/assignment2.sv
+++ b/modules/assignment2.sv
@@ -12,7 +12,7 @@
 `include "seven_seg_4digit.sv"
 
 
-module assignment2 #(width=5, romsz=10) (
+module assignment2 #(width=5, ramsz=9, romsz=10) (
 	input logic [0:0] clk
 `ifdef QUARTUS_SYNTH
     ,
@@ -79,8 +79,6 @@ module assignment2 #(width=5, romsz=10) (
     logic [2**width-1:0] rt_imm;
     sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
 
-	logic [2**width-1:0] rd_alu;
-	logic [2**width-1:0] rt_alu;
 	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags);
     assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
 
diff --git a/modules/ram.sv b/modules/ram.sv
index 17eeb3c..603fd04 100644
--- a/modules/ram.sv
+++ b/modules/ram.sv
@@ -14,7 +14,7 @@ module ram #(addrwidth=9, datawidth=5)(
 
     // NOTE: Possible issue with assignments still pending by end of initial block
     initial begin
-        for (integer ADDR = 0; ADDR < 256); ADDR = ADDR + 1) begin
+        for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
             mem[ADDR] <= 32'b0;
         end
     end