Fixed a couple bugs introduced from merge-conflict resolution

modules/assignment2.sv

@@ -12,7 +12,7 @@
 `include "seven_seg_4digit.sv"
 
 
-module assignment2 #(width=5, romsz=10) (
+module assignment2 #(width=5, ramsz=9, romsz=10) (
 	input logic [0:0] clk
 `ifdef QUARTUS_SYNTH
     ,
@@ -79,8 +79,6 @@ module assignment2 #(width=5, romsz=10) (
     logic [2**width-1:0] rt_imm;
     sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
 
-	logic [2**width-1:0] rd_alu;
-	logic [2**width-1:0] rt_alu;
 	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags);
     assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);