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Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis

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riley committed 2026-09-13 23:53:47 +10:00
1 parent 49f539c855
commit 4df723318b
2 files changed
+8 -8
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modules/alu.sv
+7 -7
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@@ -24,13 +24,13 @@ module alu #(parameter width=2)(input logic [3:0] op,
4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0100: OUT_1 = lu_out;
4'b0101: OUT_1 = lu_out;
4'b0110: OUT_1 = lu_out;
4'b0111: OUT_1 = lu_out;
4'b1010: OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1};
4'b1011: OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1};
default: OUT_1 = {(2**width){1'b0}};
4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
4'b0110: begin OUT_1 = lu_out; flags = asu_flags; end
4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
endcase
end
endmodule
modules/shifter.sv
+1 -1
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@@ -12,7 +12,7 @@ module shifter #(width=8)(input logic [2:0] op,
3'b100: OUT_1 = A << B;
3'b101: OUT_1 = A >> B;
3'b111: OUT_1 = $signed(A) >>> B;
default:;
default:OUT_1 = A;
endcase
end
endmodule