From 4df723318bf1b41034fe40b330dfee432a08c264 Mon Sep 17 00:00:00 2001 From: Riley King-Saunders Date: Sun, 13 Sep 2026 23:53:47 +1000 Subject: [PATCH] Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis --- modules/alu.sv | 14 +++++++------- modules/lu.sv | 2 +- modules/shifter.sv | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/modules/alu.sv b/modules/alu.sv index c3516ce..2687745 100644 --- a/modules/alu.sv +++ b/modules/alu.sv @@ -24,13 +24,13 @@ module alu #(parameter width=2)(input logic [3:0] op, 4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end 4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end 4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end - 4'b0100: OUT_1 = lu_out; - 4'b0101: OUT_1 = lu_out; - 4'b0110: OUT_1 = lu_out; - 4'b0111: OUT_1 = lu_out; - 4'b1010: OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; - 4'b1011: OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; - default: OUT_1 = {(2**width){1'b0}}; + 4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end + 4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end + 4'b0110: begin OUT_1 = lu_out; flags = asu_flags; end + 4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end + 4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end + 4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end + default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end endcase end endmodule diff --git a/modules/lu.sv b/modules/lu.sv index 487bc51..ce372a3 100644 --- a/modules/lu.sv +++ b/modules/lu.sv @@ -12,7 +12,7 @@ module lu #(parameter width = 2) ( 2'b01: Y = A | B; 2'b10: Y = A ^ B; 2'b11: Y = ~(A | B); - default: Y = '0; + default:Y = '0; endcase end endmodule diff --git a/modules/shifter.sv b/modules/shifter.sv index 48b1e7c..7b84b49 100644 --- a/modules/shifter.sv +++ b/modules/shifter.sv @@ -12,7 +12,7 @@ module shifter #(width=8)(input logic [2:0] op, 3'b100: OUT_1 = A << B; 3'b101: OUT_1 = A >> B; 3'b111: OUT_1 = $signed(A) >>> B; - default:; + default:OUT_1 = A; endcase end endmodule