Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis

modules/alu.sv

@@ -24,13 +24,13 @@ module alu #(parameter width=2)(input logic [3:0] op,
             4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
             4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
             4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0100: OUT_1 = lu_out;
+            4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b0101: OUT_1 = lu_out;
+            4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b0110: OUT_1 = lu_out; 
+            4'b0110: begin OUT_1 = lu_out;  flags = asu_flags; end
-            4'b0111: OUT_1 = lu_out;
+            4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b1010: OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1};
+            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
-            4'b1011: OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1};
+            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
-            default: OUT_1 = {(2**width){1'b0}};
+            default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
         endcase
     end
 endmodule

modules/shifter.sv

@@ -12,7 +12,7 @@ module shifter #(width=8)(input logic [2:0] op,
             3'b100: OUT_1 = A << B;
             3'b101: OUT_1 = A >> B;
             3'b111: OUT_1 = $signed(A) >>> B;
-            default:;
+            default:OUT_1 = A;
         endcase
     end    
 endmodule