Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis

modules/shifter.sv

@@ -12,7 +12,7 @@ module shifter #(width=8)(input logic [2:0] op,
             3'b100: OUT_1 = A << B;
             3'b101: OUT_1 = A >> B;
             3'b111: OUT_1 = $signed(A) >>> B;
-            default:;
+            default:OUT_1 = A;
         endcase
     end    
 endmodule