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Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)

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riley committed 2026-09-13 23:35:05 +10:00
1 parent 19ba1bf473
commit 49f539c855
2 files changed
+20 -30
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modules/instruction_classifier.sv
+10 -20
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@@ -1,31 +1,21 @@
`ifndef INSTRUCTION_CLASSIFIER_H_SV `ifndef INSTRUCTION_CLASSIFIER_H_SV
`define INSTRUCTION_CLASSIFIER_H_SV `define INSTRUCTION_CLASSIFIER_H_SV
// TODO: This needs to be reworked to use manual mux-ing as to ensure low gate delay
module instruction_classifier(input logic[5:0] op, module instruction_classifier(input logic[5:0] op,
output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J, output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F, output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
output logic[0:0] M); output logic[0:0] M);
always_comb begin always_comb begin
logic [6:0] OUT_1; // Performs a rolling equals check
casez (op) // Uses an AND mask to mask off bits we don't care about
6'b1?????: OUT_1 = 7'b1000000; // And a equals operator to perform a bitwise XNOR followed by a horizontal AND
6'b01????: OUT_1 = 7'b0100000; R = ( (op & 6'b111111) == 6'b000000);
6'b001???: OUT_1 = 7'b0010000; B1= ( (op & 6'b111111) == 6'b000001);
6'b0001??: OUT_1 = 7'b0001000; J = ( (op & 6'b111110) == 6'b000010);
6'b00001?: OUT_1 = 7'b0000100; B2= ( (op & 6'b111100) == 6'b000100);
6'b000001: OUT_1 = 7'b0000010; I = ( (op & 6'b111000) == 6'b001000);
6'b000000: OUT_1 = 7'b0000001; F = ( (op & 6'b110000) == 6'b010000);
default: OUT_1 = 7'bxxxxxxx; M = ( (op & 6'b100000) == 6'b100000);
endcase
R = OUT_1[6];
B1 = OUT_1[5];
J = OUT_1[4];
B2 = OUT_1[3];
I = OUT_1[2];
F = OUT_1[1];
M = OUT_1[0];
end end
endmodule endmodule
`endif `endif
tests/instruction_classifier_tb.sv
+10 -10
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@@ -10,30 +10,30 @@ module instruction_classifier_tb();
integer error_count; integer error_count;
initial begin initial begin
ops[0] = 6'b000000; ops[0] = 6'b000000;
C_exp[0] = 7'b1000000; C_exp[0] = 7'b0000001;
ops[1] = 6'b000001; ops[1] = 6'b000001;
C_exp[1] = 7'b0100000; C_exp[1] = 7'b0000010;
ops[2] = 6'b000010; ops[2] = 6'b000010;
C_exp[2] = 7'b0010000; C_exp[2] = 7'b0000100;
ops[3] = 6'b000100; ops[3] = 6'b000100;
C_exp[3] = 7'b0001000; C_exp[3] = 7'b0001000;
ops[4] = 6'b001000; ops[4] = 6'b001000;
C_exp[4] = 7'b0000100; C_exp[4] = 7'b0010000;
ops[5] = 6'b010000; ops[5] = 6'b010000;
C_exp[5] = 7'b0000010; C_exp[5] = 7'b0100000;
ops[6] = 6'b100000; ops[6] = 6'b100000;
C_exp[6] = 7'b0000001; C_exp[6] = 7'b1000000;
ops[7] = 6'b000011; ops[7] = 6'b000011;
C_exp[7] = 7'b0010000; C_exp[7] = 7'b0000100;
ops[8] = 6'b000101; ops[8] = 6'b000101;
C_exp[8] = 7'b0001000; C_exp[8] = 7'b0001000;
ops[9] = 6'b001001; ops[9] = 6'b001001;
C_exp[9] = 7'b0000100; C_exp[9] = 7'b0010000;
ops[10] = 6'b010001; ops[10] = 6'b010001;
C_exp[10] = 7'b0000010; C_exp[10] = 7'b0100000;
ops[11] = 6'b100001; ops[11] = 6'b100001;
C_exp[11] = 7'b0000001; C_exp[11] = 7'b1000000;
error_count = 0; error_count = 0;
$display("Beginning Instruction Classifier tests"); $display("Beginning Instruction Classifier tests");