From 49f539c855c1b235b6222dd5c66ad22c358f57cb Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Sun, 13 Sep 2026 23:35:05 +1000
Subject: [PATCH] Updated instruction classifier to use combinational logic
 with a depth of 3 gates (AND, XNOR, HAND)

---
 modules/instruction_classifier.sv  | 30 ++++++++++--------------------
 tests/instruction_classifier_tb.sv | 20 ++++++++++----------
 2 files changed, 20 insertions(+), 30 deletions(-)

diff --git a/modules/instruction_classifier.sv b/modules/instruction_classifier.sv
index 797ae0b..71454f1 100644
--- a/modules/instruction_classifier.sv
+++ b/modules/instruction_classifier.sv
@@ -1,31 +1,21 @@
 `ifndef INSTRUCTION_CLASSIFIER_H_SV
 `define INSTRUCTION_CLASSIFIER_H_SV
-// TODO: This needs to be reworked to use manual mux-ing as to ensure low gate delay
 module instruction_classifier(input logic[5:0] op,
     output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
     output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
     output logic[0:0] M);
 
     always_comb begin
-        logic [6:0] OUT_1;
-        casez (op)
-            6'b1?????: OUT_1 = 7'b1000000;
-            6'b01????: OUT_1 = 7'b0100000;
-            6'b001???: OUT_1 = 7'b0010000;
-            6'b0001??: OUT_1 = 7'b0001000;
-            6'b00001?: OUT_1 = 7'b0000100;
-            6'b000001: OUT_1 = 7'b0000010;
-            6'b000000: OUT_1 = 7'b0000001;
-            default:   OUT_1 = 7'bxxxxxxx;
-        endcase
-
-        R  = OUT_1[6];
-        B1 = OUT_1[5];
-        J  = OUT_1[4];
-        B2 = OUT_1[3];
-        I  = OUT_1[2];
-        F  = OUT_1[1];
-        M  = OUT_1[0];
+        // Performs a rolling equals check
+        //  Uses an AND mask to mask off bits we don't care about
+        //  And a equals operator to perform a bitwise XNOR followed by a horizontal AND 
+        R = ( (op & 6'b111111) == 6'b000000);
+        B1= ( (op & 6'b111111) == 6'b000001);
+        J = ( (op & 6'b111110) == 6'b000010);
+        B2= ( (op & 6'b111100) == 6'b000100);
+        I = ( (op & 6'b111000) == 6'b001000);
+        F = ( (op & 6'b110000) == 6'b010000);
+        M = ( (op & 6'b100000) == 6'b100000);
     end
 endmodule
 `endif
\ No newline at end of file
diff --git a/tests/instruction_classifier_tb.sv b/tests/instruction_classifier_tb.sv
index eb92f3e..2ac93c3 100644
--- a/tests/instruction_classifier_tb.sv
+++ b/tests/instruction_classifier_tb.sv
@@ -10,30 +10,30 @@ module instruction_classifier_tb();
     integer error_count;
     initial begin
         ops[0] = 6'b000000;
-        C_exp[0] = 7'b1000000;
+        C_exp[0] = 7'b0000001;
         ops[1] = 6'b000001;
-        C_exp[1] = 7'b0100000;
+        C_exp[1] = 7'b0000010;
         ops[2] = 6'b000010;
-        C_exp[2] = 7'b0010000;
+        C_exp[2] = 7'b0000100;
         ops[3] = 6'b000100;
         C_exp[3] = 7'b0001000;
         ops[4] = 6'b001000;
-        C_exp[4] = 7'b0000100;
+        C_exp[4] = 7'b0010000;
         ops[5] = 6'b010000;
-        C_exp[5] = 7'b0000010;
+        C_exp[5] = 7'b0100000;
         ops[6] = 6'b100000;
-        C_exp[6] = 7'b0000001;
+        C_exp[6] = 7'b1000000;
 
         ops[7] = 6'b000011;
-        C_exp[7] = 7'b0010000;
+        C_exp[7] = 7'b0000100;
         ops[8] = 6'b000101;
         C_exp[8] = 7'b0001000;
         ops[9] = 6'b001001;
-        C_exp[9] = 7'b0000100;
+        C_exp[9] = 7'b0010000;
         ops[10] = 6'b010001;
-        C_exp[10] = 7'b0000010;
+        C_exp[10] = 7'b0100000;
         ops[11] = 6'b100001;
-        C_exp[11] = 7'b0000001;
+        C_exp[11] = 7'b1000000;
 
         error_count = 0;
         $display("Beginning Instruction Classifier tests");