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Implemented shifter and its test bench code fully

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riley committed 2026-09-08 22:35:14 +10:00
1 parent 9794f26137
commit 42f4e661dc
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modules/shifter.sv
+8 -5
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@@ -1,12 +1,15 @@
module shifter #(width=8)(input logic op[1:0],
input logic[width-1:0] A, input logic[width-1:0] B,
module shifter #(width=8)(input logic [2:0] op,
input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
output logic[width-1:0] OUT_1);
always_comb begin
case (op)
00: OUT_1 = A << B;
01: OUT_1 = A >> B;
10: OUT_1 = $signed(A) >>> B;
3'b000: OUT_1 = A << C;
3'b001: OUT_1 = A >> C;
3'b011: OUT_1 = $signed(A) >>> C;
3'b100: OUT_1 = A << B;
3'b101: OUT_1 = A >> B;
3'b111: OUT_1 = $signed(A) >>> B;
default:;
endcase
end