diff --git a/modules/shifter.sv b/modules/shifter.sv
index e55e621..e8917d7 100644
--- a/modules/shifter.sv
+++ b/modules/shifter.sv
@@ -1,12 +1,15 @@
-module shifter #(width=8)(input logic op[1:0],
-    input logic[width-1:0] A, input logic[width-1:0] B,
+module shifter #(width=8)(input logic [2:0] op,
+    input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
     output logic[width-1:0] OUT_1);
 
     always_comb begin
         case (op)
-            00: OUT_1 = A << B;
-            01: OUT_1 = A >> B;
-            10: OUT_1 = $signed(A) >>> B;
+            3'b000: OUT_1 = A << C;
+            3'b001: OUT_1 = A >> C;
+            3'b011: OUT_1 = $signed(A) >>> C;
+            3'b100: OUT_1 = A << B;
+            3'b101: OUT_1 = A >> B;
+            3'b111: OUT_1 = $signed(A) >>> B;
             default:;
         endcase
     end    
diff --git a/tests/shifter_tb.sv b/tests/shifter_tb.sv
index 24c7945..2a43af6 100644
--- a/tests/shifter_tb.sv
+++ b/tests/shifter_tb.sv
@@ -1,5 +1,77 @@
-`#include "shifter.sv"
-
+`include "shifter.sv"
 module shifter_tb #(width=8)();
+    logic [2:0] op;
+    logic [width-1:0] Y;
+    logic [width-1:0] A_in;
+    logic [$clog2(width)-1:0] B_in;
+    logic [width-1:0] C_in;
 
+    logic [2:0] ops[6];
+    logic [width-1:0] A[6];
+    logic [$clog2(width)-1:0] B[6];
+    logic [width-1:0] C[6];
+    logic [width-1:0] Y_exp[6];
+
+    shifter #(width) dut(op, A_in,C_in,B_in,Y);
+
+    integer error_count;
+    initial begin
+        // Test left shift by C
+        ops[0] = 3'b000;
+        A[0] = {{(width-1){1'b0}}, {1'b1}};
+        C[0] = {{(width-1){1'b0}}, {1'b1}};
+        B[0] = {width{1'b0}};
+        Y_exp[0] = {{(width-2){1'b0}}, {2'b10}};
+
+        // Test left shift by B
+        ops[1] = 3'b100;
+        A[1] = {{(width-1){1'b0}}, {1'b1}};
+        C[1] = {{(width-1){1'b0}}, {1'b1}};
+        B[1] = {{($clog2(width)-2){1'b0}}, 2'b10};
+        Y_exp[1] = {{(width-3){1'b0}}, {3'b100}};
+
+        // Test Logical right shift by C
+        ops[2] = 3'b001;
+        A[2] = {{(width-2){1'b0}}, {2'b10}};
+        C[2] = {{(width-1){1'b0}}, {1'b1}};
+        B[2] = {width{1'b0}};
+        Y_exp[2] = {{(width-1){1'b0}}, {1'b1}};
+
+        // Test Logical right shift by B
+        ops[3] = 3'b101;
+        A[3] = {{(width-1){1'b0}}, {2'b10}};
+        C[3] = {{(width-1){1'b0}}, {1'b1}};
+        B[3] = {{($clog2(width)-2){1'b0}}, 2'b10};
+        Y_exp[3] = {{(width-1){1'b0}}, {1'b0}};
+
+        // Test arithmetic shift right by C
+        ops[4] = 3'b011;
+        A[4] = {{(width-1){1'b1}}, 1'b0};   // -2
+        C[4] = {{(width-1){1'b0}}, 1'b1};   // 1
+        B[4] = {{(width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[4] = {width{1'b1}};           // -1
+
+        // Test arithmetic shift right by B
+        ops[5] = 3'b111;
+        A[5] = {{(width-2){1'b1}}, 2'b00};   // -4
+        C[5] = {{(width-1){1'b0}}, 1'b1};   // 1
+        B[5] = {{(width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[5] = {width{1'b1}};           // -1
+
+        error_count = 0;
+        $display("Beginning Shifter tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op = ops[N];
+            A_in = A[N];
+            B_in = B[N];
+            C_in = C[N];
+            #1;
+            if (Y != Y_exp[N]) begin
+                $display("\t\x1b[38;5;9mShifter(%0d) Op 0b%b(0b%b, 0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N, op, A_in, B_in, C_in, Y, Y_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+        if (error_count == 0) $display("\x1b[38;5;10mAll Shifter tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d Shifter test(s) failing\x1b[m", error_count);
+    end
 endmodule
\ No newline at end of file
diff --git a/tests/tests.sv b/tests/tests.sv
index 46ea98f..abbdfa4 100644
--- a/tests/tests.sv
+++ b/tests/tests.sv
@@ -1,4 +1,5 @@
 `include "tests/seven_seg_tb.sv"
 `include "tests/lu_tb.sv"
 `include "tests/asu_tb.sv"
-`include "tests/instruction_classifier_tb.sv"
\ No newline at end of file
+`include "tests/instruction_classifier_tb.sv"
+`include "tests/shifter_tb.sv"
\ No newline at end of file