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Made RSIOut the LSB to correspond with wiring configuration

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riley committed 2026-09-03 16:56:11 +10:00
1 parent dd5d044da3
commit 3e8aa911ce
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modules/seven_seg.sv
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@@ -1,22 +1,22 @@
module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments); module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
always_comb begin always_comb begin
case (num) case (num)
4'b0000: segments = (rbi_inv) ? ~(8'b10111111) : ~(8'b00000000); 4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
4'b0001: segments = ~(8'b10000110); 4'b0001: segments = ~(8'b00001101);
4'b0010: segments = ~(8'b11011011); 4'b0010: segments = ~(8'b10110111);
4'b0011: segments = ~(8'b11001111); 4'b0011: segments = ~(8'b10011111);
4'b0100: segments = ~(8'b11100110); 4'b0100: segments = ~(8'b11001101);
4'b0101: segments = ~(8'b11101101); 4'b0101: segments = ~(8'b11011011);
4'b0110: segments = ~(8'b11111101); 4'b0110: segments = ~(8'b11111011);
4'b0111: segments = ~(8'b10000111); 4'b0111: segments = ~(8'b00001111);
4'b1000: segments = ~(8'b11111111); 4'b1000: segments = ~(8'b11111111);
4'b1001: segments = ~(8'b11100111); 4'b1001: segments = ~(8'b11001111);
4'b1010: segments = ~(8'b11110111); 4'b1010: segments = ~(8'b11101111);
4'b1011: segments = ~(8'b11111100); 4'b1011: segments = ~(8'b11111001);
4'b1100: segments = ~(8'b10111001); 4'b1100: segments = ~(8'b01110011);
4'b1101: segments = ~(8'b11011110); 4'b1101: segments = ~(8'b10111101);
4'b1110: segments = ~(8'b11111001); 4'b1110: segments = ~(8'b11110011);
4'b1111: segments = ~(8'b11110001); 4'b1111: segments = ~(8'b11100011);
default: segments = ~(8'bxxxxxxxx); default: segments = ~(8'bxxxxxxxx);
endcase endcase
end end