Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module

modules/gatereg.sv

@@ -1,5 +1,5 @@
 module gatereg #(width, ndelay=1)(
-    input logic [0:0] clk, input logic [0:0] rst, input logic en[0:0],
+    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en,
     input logic [2**width-1:0] in, output logic [2**width-1:0] out
 );
     logic [2**width-1:0] hold_value[ndelay];
@@ -7,10 +7,12 @@ module gatereg #(width, ndelay=1)(
     assign out = hold_value[ndelay-1];
     always_ff @( posedge clk ) begin
         if (rst) begin
-            hold_value <= {(2**width){0}};
+            for (integer i = 0; i < ndelay; ++i) begin
+                hold_value[i] <= {(2**width){1'b0}};
+            end
         end else if (en) begin
             hold_value[0] <= in;
-            for (int i = 1; i < ndelay; ++i) begin
+            for (integer i = 1; i < ndelay; ++i) begin
                 hold_value[i] <= hold_value[i-1];
             end
         end