TroubleElectrical/FPGA_Uni
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Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

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TroubleElectrical committed 2026-10-13 15:12:00 +11:00
1 parent 19b07b649d
commit 353923eadf
64 files changed
+386 -395
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modules/assignment2.sv
+8 -19
View File
@@ -1,25 +1,14 @@
`ifndef ASS_2_SV
`define ASS_2_SV
`ifdef SYNTHESIS
`include "../../rom.sv"
`include "../../ram.sv"
`include "../../register_file.sv"
`include "../../instruction_counter.sv"
`include "../../instruction_classifier.sv"
`include "../../instruction_module_classifier.sv"
`include "../../alu.sv"
`include "../../shifter.sv"
`else
`include "rom.sv"
`include "ram.sv"
`include "register_file.sv"
`include "instruction_counter.sv"
`include "instruction_classifier.sv"
`include "instruction_module_classifier.sv"
`include "alu.sv"
`include "shifter.sv"
`endif
`include "rom.sv"
`include "ram.sv"
`include "register_file.sv"
`include "instruction_counter.sv"
`include "instruction_classifier.sv"
`include "instruction_module_classifier.sv"
`include "alu.sv"
`include "shifter.sv"