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new file mode 100644
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new file mode 100644
index 0000000..c20e900
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diff --git a/Quartus/A2/db/assignment2.asm.qmsg b/Quartus/A2/db/assignment2.asm.qmsg
index 6039628..6ce33e6 100644
--- a/Quartus/A2/db/assignment2.asm.qmsg
+++ b/Quartus/A2/db/assignment2.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858237264 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858237264 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:23:57 2026 " "Processing started: Tue Oct 13 13:23:57 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858237264 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1791858237264 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1791858237265 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1791858237920 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1791858242577 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858242788 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:24:02 2026 " "Processing ended: Tue Oct 13 13:24:02 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858242788 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858242788 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858242788 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1791858242788 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864535759 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864535759 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:08:55 2026 " "Processing started: Tue Oct 13 15:08:55 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864535759 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1791864535759 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1791864535759 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1791864536401 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1791864540830 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864541075 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:09:01 2026 " "Processing ended: Tue Oct 13 15:09:01 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864541075 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864541075 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864541075 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1791864541075 ""}
diff --git a/Quartus/A2/db/assignment2.asm.rdb b/Quartus/A2/db/assignment2.asm.rdb
index c2890f5..3ae2ef7 100644
Binary files a/Quartus/A2/db/assignment2.asm.rdb and b/Quartus/A2/db/assignment2.asm.rdb differ
diff --git a/Quartus/A2/db/assignment2.cmp.cdb b/Quartus/A2/db/assignment2.cmp.cdb
index 972f0fe..f53a823 100644
Binary files a/Quartus/A2/db/assignment2.cmp.cdb and b/Quartus/A2/db/assignment2.cmp.cdb differ
diff --git a/Quartus/A2/db/assignment2.cmp.hdb b/Quartus/A2/db/assignment2.cmp.hdb
index 65d3d5f..d302ddf 100644
Binary files a/Quartus/A2/db/assignment2.cmp.hdb and b/Quartus/A2/db/assignment2.cmp.hdb differ
diff --git a/Quartus/A2/db/assignment2.cmp.rdb b/Quartus/A2/db/assignment2.cmp.rdb
index 5e57a07..7198c6f 100644
Binary files a/Quartus/A2/db/assignment2.cmp.rdb and b/Quartus/A2/db/assignment2.cmp.rdb differ
diff --git a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd
index b19b6d1..5b25938 100644
Binary files a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd and b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd differ
diff --git a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd
index 118df22..0778662 100644
Binary files a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd and b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd differ
diff --git a/Quartus/A2/db/assignment2.db_info b/Quartus/A2/db/assignment2.db_info
index 5ad97f3..984ea16 100644
--- a/Quartus/A2/db/assignment2.db_info
+++ b/Quartus/A2/db/assignment2.db_info
@@ -1,3 +1,3 @@
 Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Version_Index = 604268800
-Creation_Time = Tue Oct 13 13:03:37 2026
+Creation_Time = Tue Oct 13 15:07:04 2026
diff --git a/Quartus/A2/db/assignment2.eda.qmsg b/Quartus/A2/db/assignment2.eda.qmsg
index 760072d..587cf92 100644
--- a/Quartus/A2/db/assignment2.eda.qmsg
+++ b/Quartus/A2/db/assignment2.eda.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858250029 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858250030 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:24:09 2026 " "Processing started: Tue Oct 13 13:24:09 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858250030 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791858250030 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791858250030 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1791858250784 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "assignment2.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/ simulation " "Generated file assignment2.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1791858250806 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "666 " "Peak virtual memory: 666 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858250847 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:24:10 2026 " "Processing ended: Tue Oct 13 13:24:10 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858250847 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858250847 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858250847 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1791858250847 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864547964 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864547964 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:09:07 2026 " "Processing started: Tue Oct 13 15:09:07 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864547964 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791864547964 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791864547964 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1791864548683 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "assignment2.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/ simulation " "Generated file assignment2.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1791864548694 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "659 " "Peak virtual memory: 659 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864548729 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:09:08 2026 " "Processing ended: Tue Oct 13 15:09:08 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864548729 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864548729 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864548729 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1791864548729 ""}
diff --git a/Quartus/A2/db/assignment2.fit.qmsg b/Quartus/A2/db/assignment2.fit.qmsg
index 32f7ed4..c527cb1 100644
--- a/Quartus/A2/db/assignment2.fit.qmsg
+++ b/Quartus/A2/db/assignment2.fit.qmsg
@@ -1,44 +1,44 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1791858210293 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1791858210293 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "assignment2 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"assignment2\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1791858210299 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791858210371 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791858210371 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1791858210811 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1791858210862 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1791858211023 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 1 " "No exact pin location assignment(s) for 1 pins of 1 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1791858211324 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1791858218162 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858218200 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1791858218218 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791858218218 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791858218218 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1791858218219 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1791858218219 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1791858218219 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1791858218219 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1791858218219 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1791858218219 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858218231 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1791858224323 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1791858224324 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1791858224324 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1791858224327 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1791858224328 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1791858224328 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1791858224328 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1791858224332 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1791858224375 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858224856 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1791858225113 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1791858225375 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858225375 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1791858225943 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y24 X10_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36" {  } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36"} { { 12 { 0 ""} 0 24 11 13 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1791858231476 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1791858231476 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1791858231618 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1791858231618 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1791858231618 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858231621 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1791858232496 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791858232532 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791858232916 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791858232916 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791858233422 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858234687 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1336 " "Peak virtual memory: 1336 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858235491 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:23:55 2026 " "Processing ended: Tue Oct 13 13:23:55 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858235491 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:26 " "Elapsed time: 00:00:26" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858235491 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:37 " "Total CPU time (on all processors): 00:00:37" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858235491 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791858235491 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1791864510249 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1791864510249 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "assignment2 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"assignment2\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1791864510254 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791864510326 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791864510326 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1791864510728 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1791864510761 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1791864510815 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 1 " "No exact pin location assignment(s) for 1 pins of 1 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1791864511067 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1791864517541 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864517574 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1791864517576 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791864517576 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791864517576 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1791864517576 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1791864517577 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1791864517577 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1791864517577 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1791864517577 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1791864517577 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864517586 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1791864523404 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1791864523405 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1791864523405 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1791864523406 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1791864523406 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1791864523407 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1791864523407 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1791864523409 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1791864523444 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864523845 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1791864524106 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1791864524361 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864524361 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1791864524870 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y24 X10_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36" {  } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36"} { { 12 { 0 ""} 0 24 11 13 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1791864530252 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1791864530252 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1791864530413 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1791864530413 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1791864530413 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864530415 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.06 " "Total time spent on timing analysis during the Fitter is 0.06 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1791864531142 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791864531179 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791864531524 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791864531524 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791864532008 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864533291 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1336 " "Peak virtual memory: 1336 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864534048 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:08:54 2026 " "Processing ended: Tue Oct 13 15:08:54 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864534048 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Elapsed time: 00:00:25" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864534048 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:36 " "Total CPU time (on all processors): 00:00:36" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864534048 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791864534048 ""}
diff --git a/Quartus/A2/db/assignment2.hif b/Quartus/A2/db/assignment2.hif
index 76e3eea..0458485 100644
Binary files a/Quartus/A2/db/assignment2.hif and b/Quartus/A2/db/assignment2.hif differ
diff --git a/Quartus/A2/db/assignment2.map.cdb b/Quartus/A2/db/assignment2.map.cdb
index d04dd37..6bc7e92 100644
Binary files a/Quartus/A2/db/assignment2.map.cdb and b/Quartus/A2/db/assignment2.map.cdb differ
diff --git a/Quartus/A2/db/assignment2.map.hdb b/Quartus/A2/db/assignment2.map.hdb
index 63220a8..8d4db3f 100644
Binary files a/Quartus/A2/db/assignment2.map.hdb and b/Quartus/A2/db/assignment2.map.hdb differ
diff --git a/Quartus/A2/db/assignment2.map.qmsg b/Quartus/A2/db/assignment2.map.qmsg
index 45d32cf..8ae052c 100644
--- a/Quartus/A2/db/assignment2.map.qmsg
+++ b/Quartus/A2/db/assignment2.map.qmsg
@@ -1,32 +1,32 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858197350 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858197351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:23:17 2026 " "Processing started: Tue Oct 13 13:23:17 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858197351 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858197351 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858197351 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791858197661 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791858197661 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 11 11 " "Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" {  } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" {  } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" {  } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" {  } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" {  } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" {  } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" {  } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" {  } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" {  } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "11 assignment2 " "Found entity 11: assignment2" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858206828 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791858206971 ""}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(48) " "Verilog HDL or VHDL warning at assignment2.sv(48): object \"rd\" assigned a value but never read" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 48 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791858206973 "|assignment2"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" {  } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 51 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858206990 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" {  } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858206997 ""}
-{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } }  } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791858207006 "|assignment2|rom:ROM"}
-{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791858207032 "|assignment2|rom:ROM"}
-{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791858207032 "|assignment2|rom:ROM"}
-{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791858207032 "|assignment2|rom:ROM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" {  } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 53 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207036 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" {  } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 54 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207039 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" {  } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 60 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207041 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" {  } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 63 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207048 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" {  } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207054 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" {  } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207060 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" {  } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 66 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207066 ""}
-{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207119 ""}
-{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207120 ""}
-{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207121 ""}
-{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207122 ""}
-{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207124 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791858207654 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791858207721 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791858207864 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207864 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791858207996 "|assignment2|clk[0]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791858207996 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "1 " "Implemented 1 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791858207996 ""} { "Info" "ICUT_CUT_TM_OPINS" "0 " "Implemented 0 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791858207996 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791858207996 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 174 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "423 " "Peak virtual memory: 423 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858208006 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:23:28 2026 " "Processing ended: Tue Oct 13 13:23:28 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858208006 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858208006 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858208006 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858208006 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864498063 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864498064 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:08:17 2026 " "Processing started: Tue Oct 13 15:08:17 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864498064 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864498064 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864498064 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791864498375 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791864498375 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 11 11 " "Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" {  } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" {  } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" {  } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" {  } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" {  } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" {  } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" {  } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" {  } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" {  } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "11 assignment2 " "Found entity 11: assignment2" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864507414 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791864507550 ""}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(37) " "Verilog HDL or VHDL warning at assignment2.sv(37): object \"rd\" assigned a value but never read" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 37 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791864507552 "|assignment2"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" {  } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 40 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507569 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" {  } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 41 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507574 ""}
+{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } }  } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791864507583 "|assignment2|rom:ROM"}
+{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791864507607 "|assignment2|rom:ROM"}
+{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791864507607 "|assignment2|rom:ROM"}
+{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791864507608 "|assignment2|rom:ROM"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" {  } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 42 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507611 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" {  } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 43 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507614 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" {  } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 49 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507616 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" {  } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507623 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" {  } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507630 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" {  } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507635 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" {  } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 55 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507640 ""}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507688 ""}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507689 ""}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507690 ""}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507691 ""}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" {  } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507692 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791864508199 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791864508222 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791864508337 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864508337 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791864508375 "|assignment2|clk[0]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791864508375 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "1 " "Implemented 1 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791864508375 ""} { "Info" "ICUT_CUT_TM_OPINS" "0 " "Implemented 0 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791864508375 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791864508375 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 174 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "425 " "Peak virtual memory: 425 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864508386 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:08:28 2026 " "Processing ended: Tue Oct 13 15:08:28 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864508386 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864508386 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864508386 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864508386 ""}
diff --git a/Quartus/A2/db/assignment2.map.rdb b/Quartus/A2/db/assignment2.map.rdb
index aae289d..35f78e6 100644
Binary files a/Quartus/A2/db/assignment2.map.rdb and b/Quartus/A2/db/assignment2.map.rdb differ
diff --git a/Quartus/A2/db/assignment2.map_bb.cdb b/Quartus/A2/db/assignment2.map_bb.cdb
index 5e91b80..e46f7b6 100644
Binary files a/Quartus/A2/db/assignment2.map_bb.cdb and b/Quartus/A2/db/assignment2.map_bb.cdb differ
diff --git a/Quartus/A2/db/assignment2.map_bb.hdb b/Quartus/A2/db/assignment2.map_bb.hdb
index df5ce4e..dc331cc 100644
Binary files a/Quartus/A2/db/assignment2.map_bb.hdb and b/Quartus/A2/db/assignment2.map_bb.hdb differ
diff --git a/Quartus/A2/db/assignment2.pre_map.hdb b/Quartus/A2/db/assignment2.pre_map.hdb
index b460eae..e03a045 100644
Binary files a/Quartus/A2/db/assignment2.pre_map.hdb and b/Quartus/A2/db/assignment2.pre_map.hdb differ
diff --git a/Quartus/A2/db/assignment2.quiproj.5775.rdr.flock b/Quartus/A2/db/assignment2.quiproj.7676.rdr.flock
similarity index 100%
rename from Quartus/A2/db/assignment2.quiproj.5775.rdr.flock
rename to Quartus/A2/db/assignment2.quiproj.7676.rdr.flock
diff --git a/Quartus/A2/db/assignment2.rtlv.hdb b/Quartus/A2/db/assignment2.rtlv.hdb
index cee2f72..f712678 100644
Binary files a/Quartus/A2/db/assignment2.rtlv.hdb and b/Quartus/A2/db/assignment2.rtlv.hdb differ
diff --git a/Quartus/A2/db/assignment2.sta.qmsg b/Quartus/A2/db/assignment2.sta.qmsg
index 6da6962..c7c2f17 100644
--- a/Quartus/A2/db/assignment2.sta.qmsg
+++ b/Quartus/A2/db/assignment2.sta.qmsg
@@ -1,61 +1,61 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858244479 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858244480 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:24:04 2026 " "Processing started: Tue Oct 13 13:24:04 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858244480 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1791858244480 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta assignment2 -c assignment2 " "Command: quartus_sta assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1791858244480 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1791858244539 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1791858245026 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1791858245026 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858245104 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858245104 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1791858245714 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858245714 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791858245715 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791858245715 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1791858245715 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791858245715 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1791858245716 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1791858245721 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791858245721 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245723 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245734 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245735 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245736 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245736 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245737 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791858245739 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791858245784 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791858246730 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858246816 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791858246817 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791858246817 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791858246817 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246818 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246820 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246821 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246822 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246823 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246823 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791858246825 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791858247086 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791858247632 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858247668 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791858247668 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791858247669 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791858247669 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247670 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247671 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247672 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247673 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247673 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791858247675 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858247823 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791858247823 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791858247823 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791858247823 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247824 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247825 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247826 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247827 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247827 ""}
-{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" {  } {  } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791858248367 ""}
-{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" {  } {  } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791858248367 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "718 " "Peak virtual memory: 718 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858248389 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:24:08 2026 " "Processing ended: Tue Oct 13 13:24:08 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858248389 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858248389 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858248389 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1791858248389 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864542754 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864542754 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:09:02 2026 " "Processing started: Tue Oct 13 15:09:02 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864542754 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1791864542754 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta assignment2 -c assignment2 " "Command: quartus_sta assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1791864542755 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1791864542812 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1791864543269 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1791864543269 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864543339 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864543339 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1791864543906 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864543907 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791864543907 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791864543907 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1791864543908 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791864543908 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1791864543908 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1791864543912 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791864543913 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543914 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543918 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543918 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543919 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543920 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543921 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791864543923 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791864543963 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791864544799 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864544885 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791864544886 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791864544886 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791864544886 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544887 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544889 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544889 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544890 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544891 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544892 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791864544894 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791864545133 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791864545614 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864545648 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791864545648 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791864545648 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791864545648 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545649 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545650 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545651 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545652 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545652 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791864545655 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864545798 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791864545798 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791864545798 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791864545799 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545800 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545801 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545801 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545802 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545803 ""}
+{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" {  } {  } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791864546312 ""}
+{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" {  } {  } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791864546312 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "718 " "Peak virtual memory: 718 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864546330 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:09:06 2026 " "Processing ended: Tue Oct 13 15:09:06 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864546330 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864546330 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864546330 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1791864546330 ""}
diff --git a/Quartus/A2/db/assignment2.tmw_info b/Quartus/A2/db/assignment2.tmw_info
index be32990..4a8ea6c 100644
--- a/Quartus/A2/db/assignment2.tmw_info
+++ b/Quartus/A2/db/assignment2.tmw_info
@@ -1,7 +1,7 @@
-start_full_compilation:s:00:00:55
+start_full_compilation:s:00:00:52
 start_analysis_synthesis:s:00:00:12-start_full_compilation
 start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:28-start_full_compilation
+start_fitter:s:00:00:25-start_full_compilation
 start_assembler:s:00:00:07-start_full_compilation
 start_timing_analyzer:s:00:00:06-start_full_compilation
 start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/Quartus/A2/db/prev_cmp_assignment2.qmsg b/Quartus/A2/db/prev_cmp_assignment2.qmsg
index cd49738..1e094f6 100644
--- a/Quartus/A2/db/prev_cmp_assignment2.qmsg
+++ b/Quartus/A2/db/prev_cmp_assignment2.qmsg
@@ -1,15 +1,17 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858134196 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858134196 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:22:14 2026 " "Processing started: Tue Oct 13 13:22:14 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858134196 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858134196 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858134197 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791858134513 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791858134513 ""}
-{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\";  expecting a direction instruction_module_classifier.sv(10) " "Verilog HDL syntax error at instruction_module_classifier.sv(10) near text: \")\";  expecting a direction. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." {  } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 10 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791858143825 ""}
-{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "instruction_module_classifier instruction_module_classifier.sv(4) " "Ignored design unit \"instruction_module_classifier\" at instruction_module_classifier.sv(4) due to previous errors" {  } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143826 ""}
-{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "asu asu.sv(4) " "Ignored design unit \"asu\" at asu.sv(4) due to previous errors" {  } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143826 ""}
-{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "lu lu.sv(3) " "Ignored design unit \"lu\" at lu.sv(3) due to previous errors" {  } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143826 ""}
-{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "alu alu.sv(9) " "Ignored design unit \"alu\" at alu.sv(9) due to previous errors" {  } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143827 ""}
-{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "shifter shifter.sv(3) " "Ignored design unit \"shifter\" at shifter.sv(3) due to previous errors" {  } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143827 ""}
-{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(26) " "Ignored design unit \"assignment2\" at assignment2.sv(26) due to previous errors" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143827 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858143828 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 7 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 7 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858143869 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 13:22:23 2026 " "Processing ended: Tue Oct 13 13:22:23 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858143869 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858143869 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858143869 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858143869 ""}
-{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 9 s 1  " "Quartus Prime Full Compilation was unsuccessful. 9 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858144586 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864437215 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864437215 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:07:17 2026 " "Processing started: Tue Oct 13 15:07:17 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864437215 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864437215 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864437215 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791864437534 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791864437534 ""}
+{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../rom.sv assignment2.sv(5) " "Verilog HDL File I/O error at assignment2.sv(5): can't open Verilog Design File \"../../rom.sv\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 5 0 0 } }  } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446822 ""}
+{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../ram.sv assignment2.sv(6) " "Verilog HDL File I/O error at assignment2.sv(6): can't open Verilog Design File \"../../ram.sv\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 6 0 0 } }  } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""}
+{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../register_file.sv assignment2.sv(7) " "Verilog HDL File I/O error at assignment2.sv(7): can't open Verilog Design File \"../../register_file.sv\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 7 0 0 } }  } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""}
+{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_counter.sv assignment2.sv(8) " "Verilog HDL File I/O error at assignment2.sv(8): can't open Verilog Design File \"../../instruction_counter.sv\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 8 0 0 } }  } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""}
+{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_classifier.sv assignment2.sv(9) " "Verilog HDL File I/O error at assignment2.sv(9): can't open Verilog Design File \"../../instruction_classifier.sv\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 9 0 0 } }  } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446824 ""}
+{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_module_classifier.sv assignment2.sv(10) " "Verilog HDL File I/O error at assignment2.sv(10): can't open Verilog Design File \"../../instruction_module_classifier.sv\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 10 0 0 } }  } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446824 ""}
+{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../alu.sv assignment2.sv(11) " "Verilog HDL File I/O error at assignment2.sv(11): can't open Verilog Design File \"../../alu.sv\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 11 0 0 } }  } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""}
+{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../shifter.sv assignment2.sv(12) " "Verilog HDL File I/O error at assignment2.sv(12): can't open Verilog Design File \"../../shifter.sv\"" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 12 0 0 } }  } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(26) " "Ignored design unit \"assignment2\" at assignment2.sv(26) due to previous errors" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864446826 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 9 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 9 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 15:07:26 2026 " "Processing ended: Tue Oct 13 15:07:26 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864446879 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 11 s 1  " "Quartus Prime Full Compilation was unsuccessful. 11 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864447553 ""}
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb
index ada6728..41bffe8 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb differ
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb
index e4f1a6b..0a69647 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb differ
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb
index c61efd4..61098ab 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb differ
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb
index 4cd9f99..b1c9440 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb differ
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb
index dadfbd7..f84dee7 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb differ
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi
index 54d9a73..2fde693 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi differ
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb
index 6cd087e..deeee0c 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb differ
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb
index 8a1fee0..d6f8de3 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb differ
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb
index 4f4e33c..d26aee1 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb differ
diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb
index b156727..efd1672 100644
Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb differ
diff --git a/Quartus/A2/output_files/assignment2.asm.rpt b/Quartus/A2/output_files/assignment2.asm.rpt
index 6da6ab8..cd3b961 100644
--- a/Quartus/A2/output_files/assignment2.asm.rpt
+++ b/Quartus/A2/output_files/assignment2.asm.rpt
@@ -1,5 +1,5 @@
 Assembler report for assignment2
-Tue Oct 13 13:24:02 2026
+Tue Oct 13 15:09:01 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Tue Oct 13 13:24:02 2026 ;
+; Assembler Status      ; Successful - Tue Oct 13 15:09:01 2026 ;
 ; Revision Name         ; assignment2                           ;
 ; Top-level Entity Name ; assignment2                           ;
 ; Family                ; Cyclone V                             ;
@@ -78,14 +78,14 @@ on the Quartus Prime software download page.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-    Info: Processing started: Tue Oct 13 13:23:57 2026
+    Info: Processing started: Tue Oct 13 15:08:55 2026
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 521 megabytes
-    Info: Processing ended: Tue Oct 13 13:24:02 2026
-    Info: Elapsed time: 00:00:05
+    Info: Processing ended: Tue Oct 13 15:09:01 2026
+    Info: Elapsed time: 00:00:06
     Info: Total CPU time (on all processors): 00:00:05
 
 
diff --git a/Quartus/A2/output_files/assignment2.done b/Quartus/A2/output_files/assignment2.done
index cab42d9..b148955 100644
--- a/Quartus/A2/output_files/assignment2.done
+++ b/Quartus/A2/output_files/assignment2.done
@@ -1 +1 @@
-Tue Oct 13 13:24:11 2026
+Tue Oct 13 15:09:09 2026
diff --git a/Quartus/A2/output_files/assignment2.eda.rpt b/Quartus/A2/output_files/assignment2.eda.rpt
index 725337e..e0c1efb 100644
--- a/Quartus/A2/output_files/assignment2.eda.rpt
+++ b/Quartus/A2/output_files/assignment2.eda.rpt
@@ -1,5 +1,5 @@
 EDA Netlist Writer report for assignment2
-Tue Oct 13 13:24:10 2026
+Tue Oct 13 15:09:08 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Tue Oct 13 13:24:10 2026 ;
+; EDA Netlist Writer Status ; Successful - Tue Oct 13 15:09:08 2026 ;
 ; Revision Name             ; assignment2                           ;
 ; Top-level Entity Name     ; assignment2                           ;
 ; Family                    ; Cyclone V                             ;
@@ -81,13 +81,13 @@ on the Quartus Prime software download page.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-    Info: Processing started: Tue Oct 13 13:24:09 2026
+    Info: Processing started: Tue Oct 13 15:09:07 2026
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 666 megabytes
-    Info: Processing ended: Tue Oct 13 13:24:10 2026
+    Info: Peak virtual memory: 659 megabytes
+    Info: Processing ended: Tue Oct 13 15:09:08 2026
     Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01
 
diff --git a/Quartus/A2/output_files/assignment2.fit.rpt b/Quartus/A2/output_files/assignment2.fit.rpt
index 552506b..34ccd7b 100644
--- a/Quartus/A2/output_files/assignment2.fit.rpt
+++ b/Quartus/A2/output_files/assignment2.fit.rpt
@@ -1,5 +1,5 @@
 Fitter report for assignment2
-Tue Oct 13 13:23:55 2026
+Tue Oct 13 15:08:53 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -56,7 +56,7 @@ on the Quartus Prime software download page.
 +-----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                    ;
 +---------------------------------+-------------------------------------------------+
-; Fitter Status                   ; Successful - Tue Oct 13 13:23:55 2026           ;
+; Fitter Status                   ; Successful - Tue Oct 13 15:08:53 2026           ;
 ; Quartus Prime Version           ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
 ; Revision Name                   ; assignment2                                     ;
 ; Top-level Entity Name           ; assignment2                                     ;
@@ -1258,7 +1258,7 @@ Info (184021): Fitter periphery placement operations ending: elapsed time is 00:
 Info (176233): Starting register packing
 Info (176235): Finished register packing
     Extra Info (176219): No registers were packed into other blocks
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07
 Critical Warning (332012): Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
 Info (332144): No user constrained base clocks found in the design
 Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
@@ -1268,7 +1268,7 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai
 Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
 Info (170189): Fitter placement preparation operations beginning
 Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
 Info (170191): Fitter placement operations beginning
 Info (170137): Fitter placement was successful
 Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
@@ -1279,7 +1279,7 @@ Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were
     Info (170201): Optimizations that may affect the design's routability were skipped
     Info (170200): Optimizations that may affect the design's timing were skipped
 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.07 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.06 seconds.
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (334003): Started post-fitting delay annotation
@@ -1287,8 +1287,8 @@ Info (334004): Delay annotation completed successfully
 Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:02
 Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
     Info: Peak virtual memory: 1336 megabytes
-    Info: Processing ended: Tue Oct 13 13:23:55 2026
-    Info: Elapsed time: 00:00:26
-    Info: Total CPU time (on all processors): 00:00:37
+    Info: Processing ended: Tue Oct 13 15:08:54 2026
+    Info: Elapsed time: 00:00:25
+    Info: Total CPU time (on all processors): 00:00:36
 
 
diff --git a/Quartus/A2/output_files/assignment2.fit.summary b/Quartus/A2/output_files/assignment2.fit.summary
index a8c3248..ad0b928 100644
--- a/Quartus/A2/output_files/assignment2.fit.summary
+++ b/Quartus/A2/output_files/assignment2.fit.summary
@@ -1,4 +1,4 @@
-Fitter Status : Successful - Tue Oct 13 13:23:55 2026
+Fitter Status : Successful - Tue Oct 13 15:08:53 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : assignment2
 Top-level Entity Name : assignment2
diff --git a/Quartus/A2/output_files/assignment2.flow.rpt b/Quartus/A2/output_files/assignment2.flow.rpt
index 502e15c..d3dc2f5 100644
--- a/Quartus/A2/output_files/assignment2.flow.rpt
+++ b/Quartus/A2/output_files/assignment2.flow.rpt
@@ -1,5 +1,5 @@
 Flow report for assignment2
-Tue Oct 13 13:24:10 2026
+Tue Oct 13 15:09:08 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
 +-----------------------------------------------------------------------------------+
 ; Flow Summary                                                                      ;
 +---------------------------------+-------------------------------------------------+
-; Flow Status                     ; Successful - Tue Oct 13 13:24:10 2026           ;
+; Flow Status                     ; Successful - Tue Oct 13 15:09:08 2026           ;
 ; Quartus Prime Version           ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
 ; Revision Name                   ; assignment2                                     ;
 ; Top-level Entity Name           ; assignment2                                     ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 10/13/2026 13:23:17 ;
+; Start date & time ; 10/13/2026 15:08:18 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; assignment2         ;
 +-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
 +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID               ; 152226744081900.179185819706755        ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID               ; 117114050183607.179186449807774        ; --            ; --          ; --                                ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
@@ -102,11 +102,11 @@ on the Quartus Prime software download page.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:10     ; 1.0                     ; 410 MB              ; 00:00:24                           ;
-; Fitter               ; 00:00:26     ; 1.0                     ; 1336 MB             ; 00:00:36                           ;
-; Assembler            ; 00:00:05     ; 1.0                     ; 521 MB              ; 00:00:05                           ;
+; Analysis & Synthesis ; 00:00:11     ; 1.0                     ; 412 MB              ; 00:00:24                           ;
+; Fitter               ; 00:00:24     ; 1.0                     ; 1336 MB             ; 00:00:36                           ;
+; Assembler            ; 00:00:06     ; 1.0                     ; 521 MB              ; 00:00:05                           ;
 ; Timing Analyzer      ; 00:00:04     ; 1.0                     ; 718 MB              ; 00:00:04                           ;
-; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 666 MB              ; 00:00:01                           ;
+; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 659 MB              ; 00:00:01                           ;
 ; Total                ; 00:00:46     ; --                      ; --                  ; 00:01:10                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
diff --git a/Quartus/A2/output_files/assignment2.map.rpt b/Quartus/A2/output_files/assignment2.map.rpt
index 38d26ee..861d79c 100644
--- a/Quartus/A2/output_files/assignment2.map.rpt
+++ b/Quartus/A2/output_files/assignment2.map.rpt
@@ -1,5 +1,5 @@
 Analysis & Synthesis report for assignment2
-Tue Oct 13 13:23:28 2026
+Tue Oct 13 15:08:28 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -58,7 +58,7 @@ on the Quartus Prime software download page.
 +-----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                      ;
 +---------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status     ; Successful - Tue Oct 13 13:23:27 2026           ;
+; Analysis & Synthesis Status     ; Successful - Tue Oct 13 15:08:28 2026           ;
 ; Quartus Prime Version           ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
 ; Revision Name                   ; assignment2                                     ;
 ; Top-level Entity Name           ; assignment2                                     ;
@@ -440,7 +440,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-    Info: Processing started: Tue Oct 13 13:23:17 2026
+    Info: Processing started: Tue Oct 13 15:08:17 2026
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
@@ -455,200 +455,200 @@ Info (12021): Found 11 design units, including 11 entities, in source file /home
     Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3
     Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9
     Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3
-    Info (12023): Found entity 11: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26
+    Info (12023): Found entity 11: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15
 Info (12127): Elaborating entity "assignment2" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(48): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 48
-Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 51
-Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
+Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(37): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 37
+Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 40
+Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 41
 Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16
 Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
 Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
 Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
-Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 53
-Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 54
-Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 60
-Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 63
+Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 42
+Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 43
+Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 49
+Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
 Info (12128): Elaborating entity "asu" for hierarchy "alu:ALU|asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 18
 Info (12128): Elaborating entity "lu" for hierarchy "alu:ALU|lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 21
-Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 66
+Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 55
 Warning (12011): Net is missing source, defaulting to GND
-    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
+    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
 Warning (12011): Net is missing source, defaulting to GND
-    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
+    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
 Warning (12011): Net is missing source, defaulting to GND
-    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
+    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
 Warning (12011): Net is missing source, defaulting to GND
-    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
+    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
 Warning (12011): Net is missing source, defaulting to GND
-    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
-    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
+    Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
+    Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
 Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
 Info (17049): 32 registers lost all their fanouts during netlist optimizations.
 Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
     Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
 Warning (21074): Design contains 1 input pin(s) that do not drive logic
-    Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26
+    Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15
 Info (21057): Implemented 1 device resources after synthesis - the final resource count might be different
     Info (21058): Implemented 1 input pins
     Info (21059): Implemented 0 output pins
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings
-    Info: Peak virtual memory: 423 megabytes
-    Info: Processing ended: Tue Oct 13 13:23:28 2026
+    Info: Peak virtual memory: 425 megabytes
+    Info: Processing ended: Tue Oct 13 15:08:28 2026
     Info: Elapsed time: 00:00:11
-    Info: Total CPU time (on all processors): 00:00:25
+    Info: Total CPU time (on all processors): 00:00:24
 
 
diff --git a/Quartus/A2/output_files/assignment2.map.summary b/Quartus/A2/output_files/assignment2.map.summary
index 1ee9b31..fb19294 100644
--- a/Quartus/A2/output_files/assignment2.map.summary
+++ b/Quartus/A2/output_files/assignment2.map.summary
@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Tue Oct 13 13:23:27 2026
+Analysis & Synthesis Status : Successful - Tue Oct 13 15:08:28 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : assignment2
 Top-level Entity Name : assignment2
diff --git a/Quartus/A2/output_files/assignment2.sof b/Quartus/A2/output_files/assignment2.sof
index bf0a165..b532014 100644
Binary files a/Quartus/A2/output_files/assignment2.sof and b/Quartus/A2/output_files/assignment2.sof differ
diff --git a/Quartus/A2/output_files/assignment2.sta.rpt b/Quartus/A2/output_files/assignment2.sta.rpt
index f421b44..fb3c0d2 100644
--- a/Quartus/A2/output_files/assignment2.sta.rpt
+++ b/Quartus/A2/output_files/assignment2.sta.rpt
@@ -1,5 +1,5 @@
 Timing Analyzer report for assignment2
-Tue Oct 13 13:24:08 2026
+Tue Oct 13 15:09:06 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -363,7 +363,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-    Info: Processing started: Tue Oct 13 13:24:04 2026
+    Info: Processing started: Tue Oct 13 15:09:02 2026
 Info: Command: quartus_sta assignment2 -c assignment2
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -424,7 +424,7 @@ Info (332101): Design is fully constrained for setup requirements
 Info (332101): Design is fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
     Info: Peak virtual memory: 718 megabytes
-    Info: Processing ended: Tue Oct 13 13:24:08 2026
+    Info: Processing ended: Tue Oct 13 15:09:06 2026
     Info: Elapsed time: 00:00:04
     Info: Total CPU time (on all processors): 00:00:04
 
diff --git a/Quartus/A2/simulation/questa/assignment2.svo b/Quartus/A2/simulation/questa/assignment2.svo
index 79eee10..d81e8de 100644
--- a/Quartus/A2/simulation/questa/assignment2.svo
+++ b/Quartus/A2/simulation/questa/assignment2.svo
@@ -17,7 +17,7 @@
 // PROGRAM "Quartus Prime"
 // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
 
-// DATE "10/13/2026 13:24:10"
+// DATE "10/13/2026 15:09:08"
 
 // 
 // Device: Altera 5CGXFC5C6F27C7 Package FBGA672
diff --git a/modules/assignment2.sv b/modules/assignment2.sv
index fff260b..d462d96 100644
--- a/modules/assignment2.sv
+++ b/modules/assignment2.sv
@@ -1,25 +1,14 @@
 `ifndef ASS_2_SV
 `define ASS_2_SV
 
-`ifdef SYNTHESIS
-	`include "../../rom.sv"
-    `include "../../ram.sv"
-    `include "../../register_file.sv"
-    `include "../../instruction_counter.sv"
-    `include "../../instruction_classifier.sv"
-    `include "../../instruction_module_classifier.sv"
-    `include "../../alu.sv"
-    `include "../../shifter.sv"
-`else
-	`include "rom.sv"
-    `include "ram.sv"
-    `include "register_file.sv"
-    `include "instruction_counter.sv"
-    `include "instruction_classifier.sv"
-    `include "instruction_module_classifier.sv"
-    `include "alu.sv"
-    `include "shifter.sv"
-`endif
+`include "rom.sv"
+`include "ram.sv"
+`include "register_file.sv"
+`include "instruction_counter.sv"
+`include "instruction_classifier.sv"
+`include "instruction_module_classifier.sv"
+`include "alu.sv"
+`include "shifter.sv"