TroubleElectrical/FPGA_Uni
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Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

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TroubleElectrical committed 2026-10-13 15:12:00 +11:00
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commit 353923eadf
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Quartus/A2/simulation/questa/assignment2.svo
+1 -1
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@@ -17,7 +17,7 @@
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
// DATE "10/13/2026 13:24:10"
// DATE "10/13/2026 15:09:08"
//
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672