TroubleElectrical/FPGA_Uni
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Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

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TroubleElectrical committed 2026-10-13 15:12:00 +11:00
1 parent 19b07b649d
commit 353923eadf
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+386 -395
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Quartus/A2/output_files/assignment2.flow.rpt
+8 -8
View File
@@ -1,5 +1,5 @@
Flow report for assignment2
Tue Oct 13 13:24:10 2026
Tue Oct 13 15:09:08 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Oct 13 13:24:10 2026 ;
; Flow Status ; Successful - Tue Oct 13 15:09:08 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/13/2026 13:23:17 ;
; Start date & time ; 10/13/2026 15:08:18 ;
; Main task ; Compilation ;
; Revision Name ; assignment2 ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 152226744081900.179185819706755 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 117114050183607.179186449807774 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -102,11 +102,11 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 410 MB ; 00:00:24 ;
; Fitter ; 00:00:26 ; 1.0 ; 1336 MB ; 00:00:36 ;
; Assembler ; 00:00:05 ; 1.0 ; 521 MB ; 00:00:05 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 412 MB ; 00:00:24 ;
; Fitter ; 00:00:24 ; 1.0 ; 1336 MB ; 00:00:36 ;
; Assembler ; 00:00:06 ; 1.0 ; 521 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:04 ; 1.0 ; 718 MB ; 00:00:04 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 659 MB ; 00:00:01 ;
; Total ; 00:00:46 ; -- ; -- ; 00:01:10 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+