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Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

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TroubleElectrical committed 2026-10-13 15:12:00 +11:00
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Quartus/A2/db/prev_cmp_assignment2.qmsg
+17 -15
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@@ -1,15 +1,17 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858134196 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858134196 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:22:14 2026 " "Processing started: Tue Oct 13 13:22:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858134196 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858134196 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858134197 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791858134513 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791858134513 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting a direction instruction_module_classifier.sv(10) " "Verilog HDL syntax error at instruction_module_classifier.sv(10) near text: \")\"; expecting a direction. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 10 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791858143825 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "instruction_module_classifier instruction_module_classifier.sv(4) " "Ignored design unit \"instruction_module_classifier\" at instruction_module_classifier.sv(4) due to previous errors" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143826 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "asu asu.sv(4) " "Ignored design unit \"asu\" at asu.sv(4) due to previous errors" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143826 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "lu lu.sv(3) " "Ignored design unit \"lu\" at lu.sv(3) due to previous errors" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143826 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "alu alu.sv(9) " "Ignored design unit \"alu\" at alu.sv(9) due to previous errors" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143827 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "shifter shifter.sv(3) " "Ignored design unit \"shifter\" at shifter.sv(3) due to previous errors" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143827 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(26) " "Ignored design unit \"assignment2\" at assignment2.sv(26) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143827 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858143828 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 7 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 7 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858143869 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 13:22:23 2026 " "Processing ended: Tue Oct 13 13:22:23 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858143869 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858143869 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858143869 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858143869 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 9 s 1 " "Quartus Prime Full Compilation was unsuccessful. 9 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858144586 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864437215 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864437215 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:07:17 2026 " "Processing started: Tue Oct 13 15:07:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864437215 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864437215 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864437215 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791864437534 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791864437534 ""}
{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../rom.sv assignment2.sv(5) " "Verilog HDL File I/O error at assignment2.sv(5): can't open Verilog Design File \"../../rom.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 5 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446822 ""}
{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../ram.sv assignment2.sv(6) " "Verilog HDL File I/O error at assignment2.sv(6): can't open Verilog Design File \"../../ram.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 6 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""}
{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../register_file.sv assignment2.sv(7) " "Verilog HDL File I/O error at assignment2.sv(7): can't open Verilog Design File \"../../register_file.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 7 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""}
{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_counter.sv assignment2.sv(8) " "Verilog HDL File I/O error at assignment2.sv(8): can't open Verilog Design File \"../../instruction_counter.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 8 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""}
{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_classifier.sv assignment2.sv(9) " "Verilog HDL File I/O error at assignment2.sv(9): can't open Verilog Design File \"../../instruction_classifier.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 9 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446824 ""}
{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_module_classifier.sv assignment2.sv(10) " "Verilog HDL File I/O error at assignment2.sv(10): can't open Verilog Design File \"../../instruction_module_classifier.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 10 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446824 ""}
{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../alu.sv assignment2.sv(11) " "Verilog HDL File I/O error at assignment2.sv(11): can't open Verilog Design File \"../../alu.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 11 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""}
{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../shifter.sv assignment2.sv(12) " "Verilog HDL File I/O error at assignment2.sv(12): can't open Verilog Design File \"../../shifter.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 12 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(26) " "Ignored design unit \"assignment2\" at assignment2.sv(26) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864446826 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 9 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 9 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 15:07:26 2026 " "Processing ended: Tue Oct 13 15:07:26 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864446879 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 11 s 1 " "Quartus Prime Full Compilation was unsuccessful. 11 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864447553 ""}